• 전자공학회논문지
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• 제49권12호
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• pp.226-233
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• 2012

본 논문에서는 고속 인터페이스 비트오류율(BER, Bit Error Rate)의 수학적 모델을 기반으로, 간단하고 정확하게 시간마진을 추정할 수 있는 '선형 근사화 추정법(linear approximation method)'을 제안하였다. 기존의 Q-factor를 이용한 추정법과 제안한 선형 근사화 추정법을 이용하여 $10^{-13}$ 이하의 BER을 얻기 위한 시간마진을 추정한 결과는 실측한 값과 비교할 때 약 0.03UI 정도의 작은 오차를 갖는다. 이 중 선형 근사화를 이용한 가속 자가내장측정법(built-in self test)을 내부 BERT(BER Tester)를 포함한 하드웨어로 구현하였다. 3Gbps, 95% 신뢰 수준에서 $10^{-13}$ BER 기준의 시간마진을 직접 측정하는데 소요되는 시간이 약 5.6시간인데 반해, 가속 자가내장측정법은 0.6초 이내에 유사한 정확도로 시간마진을 추정한다. 시간마진 추정치는 시간마진을 내부 BERT로 직접 측정한 값과 0.045UI 이하의 작은 오차를 보였다.

• 전기학회논문지
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• 제57권6호
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• pp.1081-1086
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• 2008

This paper presents the $3^{rd}$ 4bit sigma delta modulator with the block and timing diagrams of DWA(Data Weighted Averaging) to optimize a operating time. In the modulator, the proposed DWA structure has a stable operation and timing margin so as to remove three latches and another clock. Because the modulator with proposed DWA structure improve timing margin about 23%. It can increase sampling frequency up to 244MHz. Through the MATLAB modeling, the optimized coefficients are obtained to design the modulator. The fully differential SC integrators, DAC, switch, quantizer, and DWA are designed by considering the nonideal characteristics. The designed $3^{rd}$ order 4bit modulator has a power consumption of 40mW and SNR(signal to noise ratio) of 77.2dB under 1.2V supply and 64MHz sampling frequency.

• 에너지공학
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• 제19권1호
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• pp.32-38
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• 2010

The objective of the research was to study the effects a Miller cycle. The engine was dedicated to natural gas usage by modifying pistons, fuel system and ignition systems. The engine was installed on a dynamometer and attached with various sensors and controllers. Intake valve timing, engine speed, load, injection timing and ignition timing are main parameters. Miller Cycle without supercharging can increase brake thermal efficiency 1.08% and reduce brake specific fuel consumption 4.58%. The injection timing must be synchronous with valve timing, speed and load to control the performances, emissions and knock margin. Throughout these tested speeds, original camshaft is recommended to obtain high volumetric efficiency.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제51권11호
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• pp.541-545
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• 2002

This paper proposes the new narrow erase method to erase wall charges formed in an AC plasma display panel (PDP) cell. In the proposed method, pulse timing of switch at the sustain period is adjusted for inducing, a weak discharge. Then, after the narrow erase, the voltage of the X electrode is set to differ from that of the Y electrode. For the proposed method, the measured maximum address voltage margin was 38.3V at Y_Rest voltage of 100V and sustain voltage of 180${\sim}$185V. However, for the conventional method, in which the X and Y electrodes are set to be of equal voltage after the narrow erase, the measured maximum address voltage margin was 31.3V at Y_Rest voltage of 150V and sustain voltage of 180V. This result shows that the measured maximum voltage margin for the proposed method is about 7V(22%) higher than that for the conventional method.

• 에너지공학
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• 제17권4호
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• pp.198-203
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• 2008

The objective of the research was to study the effects of Miller cycle in a modified using diesel engine. The engine was dedicated to natural gas usage by modifying pistons, fuel system and ignition systems. The engine was installed on a dynamometer and attached with various sensors and controllers. Intake valve timing, engine speed, load, injection timing and ignition timing are main parameters. The results of engine performances and emissions are present in form of graphs. Miller Cycle without supercharging can increase brake thermal efficiency and reduce brake specific fuel consumption. The injection timing must be synchronous with valve timing, speed and load to control the performances, emissions and knock margin. Throughout these tested speeds, original camshaft is recommended to obtain high volumetric efficiency. Retard ignition timing can reduce $NO_x$ emissions while maintaining high efficiency.

• Nuclear Engineering and Technology
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• 제48권3호
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• pp.684-701
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• 2016

The Gaussian process model (GPM) is a flexible surrogate model that can be used for nonparametric regression for multivariate problems. A unique feature of the GPM is that a prediction variance is automatically provided with the regression function. In this paper, we estimate the safety margin of a nuclear power plant by performing regression on the output of best-estimate simulations of a large-break loss-of-coolant accident with sampling of safety system configuration, sequence timing, technical specifications, and thermal hydraulic parameter uncertainties. The key aspect of our approach is that the GPM regression is only performed on the dominant input variables, the safety injection flow rate and the delay time for AC powered pumps to start representing sequence timing uncertainty, providing a predictive model for the peak clad temperature during a reflood phase. Other uncertainties are interpreted as contributors to the measurement noise of the code output and are implicitly treated in the GPM in the noise variance term, providing local uncertainty bounds for the peak clad temperature. We discuss the applicability of the foregoing method to reduce the use of conservative assumptions in best estimate plus uncertainty (BEPU) and Level 1 probabilistic safety assessment (PSA) success criteria definitions while dealing with a large number of uncertainties.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.11-22
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• 2016

Clock skew scheduling is one of the essential steps to be carefully performed during the design process. This work addresses the clock skew optimization problem integrated with the consideration of the inter-dependent relation between the setup and hold times, and clock to-Q delay of flip-flops, so that the time margin is more accurately and reliably set aside over that of the previous methods, which have never taken the integrated problem into account. Precisely, based on an accurate flexible model of setup time, hold time, and clock-to-Q delay, we propose a stepwise clock skew scheduling technique in which at each iteration, the worst slack of setup and hold times is systematically and incrementally relaxed to maximally extend the time margin. The effectiveness of the proposed method is shown through experiments with benchmark circuits, demonstrating that our method relaxes the worst slack of circuits, so that the clock period ($T_{clk}$) is shortened by 4.2% on average, namely the clock speed is improved from 369 MHz~2.23 GHz to 385 MHz~2.33 GHz with no time violation. In addition, it reduces the total numbers of setup and hold time violations by 27.7%, 9.5%, and 6.7% when the clock periods are set to 95%, 90%, and 85% of the value of Tclk, respectively.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2013년도 추계학술대회
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• pp.386-389
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• 2013

본 논문에서는 Processor와 DDR2 사이에 인터페이스되는 고속신호의 Signal Integrity 해석을 위해 IC Chip의 IBIS Model과 Transmission Line의 S-Parameter를 이용하여 고속신호의 Transient 해석을 수행하고 Eye Diagram을 생성하였다. 고속으로 동작하는 DQ, DQS/DQSb 신호 및 Clock, Address, Control 신호의 Eye Diagram에서 Setup/Hold 구간동안 Timing Margin과 Voltage Margin을 측정하였으며 Over-/Under-shoot 및 Differential 신호의 Cross Point가 Spec에 만족하는지 확인하여 신호의 품질을 확보하였다.

• 전기전자학회논문지
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• 제23권3호
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• pp.1046-1053
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• 2019

멀티채널 단일 종단(single-ended) 환경에서 채널 사이의 상호인덕턴스 및 상호캐패시턴스에 의한 원단누화 현상(FEXT)은 결정적으로 채널의 대역폭 감소를 일으킨다. 원단누화에 의해 누화-유발 지터(CIJ)와 누화-유발 글리치(CIG)가 생기며 이들은 각각 타이밍 마진 감소와 전압 마진 감소를 일으킨다. 따라서 아이 오프닝 증가와 높은 데이터 전송속도를 얻기 위해서는 원단누화 현상을 보상해야 한다. 원단누화 보상은 송신단에서 타이밍 조절 또는 파형 변형을 통해 보상할 수 있다. 또한, 수신단에서 고역-필터를 사용하여 유사 원단누화 잡음을 만들어 보상하는 방법도 있다. 본 논문에서는 원단누화 보상의 최근 기술 동향을 소개하며, 이들의 장점과 단점을 논의한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권1호
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• pp.37-50
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• 2009

Evaluation results about area scaling capabilities of various SRAM margin-assist techniques for random $V_T$ variability issues are described. Various efforts to address these issues by not only the cell topology changes from 6T to 8T and 10T but also incorporating multiple voltage-supply for the cell terminal biasing and timing sequence controls of read and write are comprehensively compared in light of an impact on the required area overhead for each design solution given by ever increasing $V_T$ variation (${\sigma}_{VT}$). Two different scenarios which hinge upon the EOT (Effective Oxide Thickness) scaling trend of being pessimistic and optimistic, are assumed to compare the area scaling trends among various SRAM solutions for 32 nm process node and beyond. As a result, it has been shown that 6T SRAM will be allowed long reign even in 15 nm node if ${\sigma}_{VT}$ can be suppressed to < 70 mV thanks to EOT scaling for LSTP (Low Standby Power) process.