• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.226-233
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• 2012

In this paper, we propose a 'linear approximation method' which is an accelerated BER (Bit Error Rate) test method for high speed interfaces, based on an analytical BER model. Both the conventional 'Q-factor estimation method' and 'linear approximation method' can predict a timing margin for $10^{-13}$ BER with an error of about 0.03UI. This linear approximation method is implemented on a hardware as an accelerated Built-In Self Test (BIST) with an internal BERT (BET Tester). While a direct measurement of a timing margin in a 3Gbps interface takes about 5.6 hours with $10^{-13}$ BER requirement and 95% confidence level, the accelerated BIST estimates a timing margin within 0.6 second without a considerable loss of accuracy. The test results show that the error between the estimated timing margin and the timing margin from an actual measurement using the internal BERT is less than 0.045UI.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.6
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• pp.1081-1086
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• 2008

This paper presents the $3^{rd}$ 4bit sigma delta modulator with the block and timing diagrams of DWA(Data Weighted Averaging) to optimize a operating time. In the modulator, the proposed DWA structure has a stable operation and timing margin so as to remove three latches and another clock. Because the modulator with proposed DWA structure improve timing margin about 23%. It can increase sampling frequency up to 244MHz. Through the MATLAB modeling, the optimized coefficients are obtained to design the modulator. The fully differential SC integrators, DAC, switch, quantizer, and DWA are designed by considering the nonideal characteristics. The designed $3^{rd}$ order 4bit modulator has a power consumption of 40mW and SNR(signal to noise ratio) of 77.2dB under 1.2V supply and 64MHz sampling frequency.

• Journal of Energy Engineering
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• v.19 no.1
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• pp.32-38
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• 2010

The objective of the research was to study the effects a Miller cycle. The engine was dedicated to natural gas usage by modifying pistons, fuel system and ignition systems. The engine was installed on a dynamometer and attached with various sensors and controllers. Intake valve timing, engine speed, load, injection timing and ignition timing are main parameters. Miller Cycle without supercharging can increase brake thermal efficiency 1.08% and reduce brake specific fuel consumption 4.58%. The injection timing must be synchronous with valve timing, speed and load to control the performances, emissions and knock margin. Throughout these tested speeds, original camshaft is recommended to obtain high volumetric efficiency.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.11
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• pp.541-545
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• 2002

This paper proposes the new narrow erase method to erase wall charges formed in an AC plasma display panel (PDP) cell. In the proposed method, pulse timing of switch at the sustain period is adjusted for inducing, a weak discharge. Then, after the narrow erase, the voltage of the X electrode is set to differ from that of the Y electrode. For the proposed method, the measured maximum address voltage margin was 38.3V at Y_Rest voltage of 100V and sustain voltage of 180${\sim}$185V. However, for the conventional method, in which the X and Y electrodes are set to be of equal voltage after the narrow erase, the measured maximum address voltage margin was 31.3V at Y_Rest voltage of 150V and sustain voltage of 180V. This result shows that the measured maximum voltage margin for the proposed method is about 7V(22%) higher than that for the conventional method.

• Journal of Energy Engineering
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• v.17 no.4
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• pp.198-203
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• 2008

The objective of the research was to study the effects of Miller cycle in a modified using diesel engine. The engine was dedicated to natural gas usage by modifying pistons, fuel system and ignition systems. The engine was installed on a dynamometer and attached with various sensors and controllers. Intake valve timing, engine speed, load, injection timing and ignition timing are main parameters. The results of engine performances and emissions are present in form of graphs. Miller Cycle without supercharging can increase brake thermal efficiency and reduce brake specific fuel consumption. The injection timing must be synchronous with valve timing, speed and load to control the performances, emissions and knock margin. Throughout these tested speeds, original camshaft is recommended to obtain high volumetric efficiency. Retard ignition timing can reduce $NO_x$ emissions while maintaining high efficiency.

• Nuclear Engineering and Technology
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• v.48 no.3
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• pp.684-701
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• 2016

The Gaussian process model (GPM) is a flexible surrogate model that can be used for nonparametric regression for multivariate problems. A unique feature of the GPM is that a prediction variance is automatically provided with the regression function. In this paper, we estimate the safety margin of a nuclear power plant by performing regression on the output of best-estimate simulations of a large-break loss-of-coolant accident with sampling of safety system configuration, sequence timing, technical specifications, and thermal hydraulic parameter uncertainties. The key aspect of our approach is that the GPM regression is only performed on the dominant input variables, the safety injection flow rate and the delay time for AC powered pumps to start representing sequence timing uncertainty, providing a predictive model for the peak clad temperature during a reflood phase. Other uncertainties are interpreted as contributors to the measurement noise of the code output and are implicitly treated in the GPM in the noise variance term, providing local uncertainty bounds for the peak clad temperature. We discuss the applicability of the foregoing method to reduce the use of conservative assumptions in best estimate plus uncertainty (BEPU) and Level 1 probabilistic safety assessment (PSA) success criteria definitions while dealing with a large number of uncertainties.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.11-22
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• 2016

Clock skew scheduling is one of the essential steps to be carefully performed during the design process. This work addresses the clock skew optimization problem integrated with the consideration of the inter-dependent relation between the setup and hold times, and clock to-Q delay of flip-flops, so that the time margin is more accurately and reliably set aside over that of the previous methods, which have never taken the integrated problem into account. Precisely, based on an accurate flexible model of setup time, hold time, and clock-to-Q delay, we propose a stepwise clock skew scheduling technique in which at each iteration, the worst slack of setup and hold times is systematically and incrementally relaxed to maximally extend the time margin. The effectiveness of the proposed method is shown through experiments with benchmark circuits, demonstrating that our method relaxes the worst slack of circuits, so that the clock period ($T_{clk}$) is shortened by 4.2% on average, namely the clock speed is improved from 369 MHz~2.23 GHz to 385 MHz~2.33 GHz with no time violation. In addition, it reduces the total numbers of setup and hold time violations by 27.7%, 9.5%, and 6.7% when the clock periods are set to 95%, 90%, and 85% of the value of Tclk, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.386-389
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• 2013

In this paper, for signal integrity analysing high-speed signal between a processor and a DDR2 memory, transient analysis is done and eye diagrams are generated using IBIS models of IC chips and S-parameters of transmission line. From the eye diagrams of such high-speed signals as DQ, DQS/DQSb, Clock, Address and Control, signal quality is assured through measuring timing and voltage margins during setup and hold times and verifying that the over-/under-shoot and the cross points of differential signals satisfy their specifications.

• Journal of IKEEE
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• v.23 no.3
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• pp.1046-1053
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• 2019

In a multi-channel single-ended system, the far-end crosstalk (FEXT) due to mutual inductance and mutual capacitance between two adjacent channels critically limit the bandwidth. FEXT causes crosstalk-induced jitter (CIJ) and crosstalk-induced glitch (CIG) which leads to timing margin and voltage margin degradations, respectively. Therefore, FEXT must be compensated in order to increase eye opening and achieve high data-rate. It can be compensated in transmitter by controlling the timing of the data or reshaping the waveform of the signal. Also, FEXT can be compensated in receiver by generating mimicked FEXT using high-pass filter. In this paper, recent techniques to compensate FEXT are investigated, with discussions of their pros and cons.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.37-50
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• 2009

Evaluation results about area scaling capabilities of various SRAM margin-assist techniques for random $V_T$ variability issues are described. Various efforts to address these issues by not only the cell topology changes from 6T to 8T and 10T but also incorporating multiple voltage-supply for the cell terminal biasing and timing sequence controls of read and write are comprehensively compared in light of an impact on the required area overhead for each design solution given by ever increasing $V_T$ variation (${\sigma}_{VT}$). Two different scenarios which hinge upon the EOT (Effective Oxide Thickness) scaling trend of being pessimistic and optimistic, are assumed to compare the area scaling trends among various SRAM solutions for 32 nm process node and beyond. As a result, it has been shown that 6T SRAM will be allowed long reign even in 15 nm node if ${\sigma}_{VT}$ can be suppressed to < 70 mV thanks to EOT scaling for LSTP (Low Standby Power) process.