• 전기학회논문지
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• 제62권3호
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• pp.395-400
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• 2013

In this paper, we introduce the implementation of high accurate level sensor system using the pulse wave type magnetostriction sensor. When a current pulse flows along the waveguide, the magnetic field also propagates towards the end of waveguide. When this magnetic field just passes the position of the magnet for level detection, the resultant magnetic field by these two magnetic fields makes a torsional reflected signal. This is used to calculate the time difference between a interrogation pulse wave and this torsional reflected signal. The key elements and characteristics were investigated to implement level sensor system based on this principle. We introduce a method to calculate the speed of ultrasonic reflected signal and how to make a model of sensing coil. In particular, we experiment with the characteristics of the torsional reflected signal according to the changes of the interrogation voltage and displacement. To make high accurate level sensor system, two methods were compared. One is to use the comparator and time counter, the other is STFT(Short Time FFT) which is capable of the time-frequency analysis.

• 전자공학회논문지
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• 제53권2호
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• pp.141-146
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• 2016

본 논문에서는 비동기식 통신 시스템에서 시간격 오차를 개선하기 위한 기법을 연구하였다. 최대 시간격 오차를 유지하기 위한 방법을 제안하기 위하여 다중 위상 전압 제어 발진기와 보간기, 위상 선택기, 업-다운 카운터, 비교기, 덧셈기를 이용하여 주파수 변조기를 설계하고 모의실험을 수행하였다. 비동기식 CAN 통신에 사용하는 클록을 변조하는 모의실험 결과, 최대 시간격 오차는 허용치 보다 낮게 유지할 수 있는 것을 확인할 수 있었다. 본 논문에서 제안한 주파수 변조 기법은 다중 위상 선택에 의한 주파수 변조 기법을 주축으로 하고 있으며, 높은 신뢰도가 요구되는 비동기식 통신 시스템의 구현에 효과적으로 적용 가능할 것으로 기대한다.

• 한국정보통신학회논문지
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• 제13권5호
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• pp.1030-1037
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• 2009

현재 SAW 센서는 많은 발전을 해왔고 온도나 압력용 SAW 센서를 저전력, 고속 신호 처리로 하기 위해서는 TDS(Time Domain Sampling) 방식을 이용한 리더기 플랫폼이 필요하다. 이러한 리더기를 제작하기 위해서는 SAW 센서의 표준 응답신호와의 변화된 응답시간과의 짧은 시간차를 측정하기 위해 고속의 타이머가 필요하게 된다. 여기서 제안하는 플랫폼은 SAW 센서에 신호를 받아서 비교기로 아날로그 신호를 디지털 신호로 전환하여 그 전환된 신호를 타이머 모듈에서 읽어 들여 신호들의 시간차를 측정하여 표시하여 나노초(Nano Second) 단위의 시간을 측정하는 방법을 제안 하고자 한다.

• Journal of Advanced Marine Engineering and Technology
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• 제19권3호
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• pp.91-98
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• 1995

To control speed or torque of induction motors, scalar control method that regulates the value of stator current had been used conventionally. But, vector control method which contrls the direction and the value of stator current at the same time has been introduced lately and employed widely. This paper describes comparative analyses of above two methods by computer simulation. As a result of the simulation, both methods showed good responses for high speed, but, vector control method characterized much better performance for low speed and sinusoidal input.

• Journal of information and communication convergence engineering
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• 제7권1호
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• pp.62-65
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• 2009

In this paper, the temperature characteristics of full CMOS FLL(frequency locked loop) re analyzed. The FLL circuit is used to generate an output signal that tracks an input efference signal. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. Also the FLL s designed to allow the circuit to be fully integrated. The FLL circuit is composed two VCs, two buffers, a VCO and two frequency dividers. The temperature variation of frequency divider, FVC and buffer cancelled because the circuit structure. is the same and he temperature effect is cancelled by the comparator. Simulation results are shown to illustrate the performance of the designed FLL circuit with temperature.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.35-41
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• 2017

We propose a novel multi-photodiode array (MPDA) based retinal implant IC with on/off stimulation strategy for a visual prosthesis with improved spatial resolution. An active pixel sensor combined with a comparator enables generation of biphasic current pulses when light intensity meets a threshold condition. The threshold is tuned by changing the discharging time of the active pixel sensor for various light intensity environments. A prototype of the 30-channel retinal implant IC was fabricated with a unit pixel area of $0.021mm^2$, and the stimulus level up to $354{\mu}A$ was measured with the threshold ranging from 400 lx to 13120 lx.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1989년도 추계학술대회 논문집 학회본부
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• pp.310-312
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• 1989

From the viewpoint of an effective energy use, many method for reactive power compensation has been developed. Among of the reactive power compensation, this paper describes the relation of operation interpretation, filter, hysteresis width and switching time of current controlled PWM converter which has excellent reactive power compensation. This current controlled PWM convertor is excellent the view of reactive power compensation by current control method using hysteresis comparator method, but is required element of high response characteristics. Therefore this paper offers the series of data for system considering switching characteristics of switching element.

• ETRI Journal
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• 제17권2호
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• pp.21-30
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• 1995

A new architecture of field programmable gate array for high-speed datapath applications is presented. Its implementation is facilitated by a configurable interconnect technology based on a one-time, two-terminal programmable, very low-impedance anti-fuse and by a configurable logic module optimized for datapath applications. The configurable logic module can effectively implement diverse logic functions including sequential elements such as latches and flip-flops, and arithmetic functions such as one-bit full adder and two-bit comparator. A novel programming architecture is designed for supplying large current through the anti-fuse element, which drops the on-resistance of anti-fuse below $20{\Omega}$. The chip has been fabricated using a $0.8-{\mu}m$ n-well complementary metal oxide semiconductor technology with two layers of metalization.

• 한국통신학회논문지
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• 제32권10C호
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• pp.1019-1024
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• 2007

본 논문에서는 무선 랜 시스템용 10비트 20MHz 파이프라인 아날로그-디지털 변환기 설계를 위해서 Verilog-A 언어를 사용하여서 모델링하였다. 변환기내 샘플 / 홀드 증폭기, 비교기, MDAC 및 오차 보정 회로 등의 구성회로들을 각각 모델링해서 모의실험 한 결과 HSPICE를 이용한 모의 실험 시간보다 1/50배로 단축되어서 시스템 모델링에 적합함을 확인하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 A
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• pp.271-274
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• 2003

This paper presents a Built-in Current Sensor that detect defects in CMOS integrated circuits using the current testing technique. This scheme employs a cross-coupled connected PMOS transistors, it is used as a current comparator. Our proposed scheme is a negligible impart on the performance of the circuit undo. test (CUT). In addition, in the normal mode of the CUT not dissipation extra power, high speed detection time and applicable deep submicron process. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects. The entire area of the test chip is $116{\times}65{\mu}m^2$. The BICS occupies only $41{\times}17{\mu}m^2$ of area in the test chip. The area overhead of a BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix $0.35{\mu}m$ 2-poly 4-metal N-well CMOS technology.