• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2017년도 추계학술대회
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• pp.520-521
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• 2017

일반적인 카운터 타입의 시간-디지털 변환기에서 시간간격 신호와 클록신호의 비동기로 인하여 디지털 변환에러가 발생한다. 클록의 주기를 $T_{CLOCK}$라고 하면, 시간간격 신호의 시작신호와 클록의 비동기로 인하여 최대 $T_{CLOCK}$의 변환에러가 발생한다. 그리고 시간간격 신호의 멈춤신호와 클록의 비동기로 인하여 최대 $-T_{CLOCK}$의 변환에러가 발생한다. 그러나 시작신호와 클록을 동기화하고 클록을 시간간격 신호동안 발생시킬 경우 디지털 변환에러의 범위는 0에서 $(1/2)T_{CLOCK}$이다.

• 천문학논총
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• 제28권2호
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• pp.17-23
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• 2013

Song I-Yeong (1619 ~ 1692), who was an astronomy professor of Gwansanggam (觀象監, Bureau of Astronomy), created the Honcheonsigye (渾天時計, Armillary Clock) in 1669 (10th year of King Hyeonjong Era). Honcheonsigye was a unique astronomical clock which combined an armillary sphere, the traditional astronomical instrument of the Far East, with the power mechanism of western alarm clock. The clock part of this armillary clock is composed of two major parts which are the going-train, power unit used the weight, and the time signal system in a wooden case. The time signal system is composed of four parts which are the time-annunciator, the striking train, the 12 different time-announcing medallions and the sound bell. This clock has been neglected for many years and its several components have been lost. This study is to understand the structure of time signal system and suggests the restoration process.

• 대한임베디드공학회논문지
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• 제12권4호
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• pp.239-246
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• 2017

Time synchronization between distributed embedded systems in the Real Time Locating System (RTLS) based on Time Difference of Arrival (TDOA) is one of the most important factors to consider in system design. Clock jitter error between each system causes many difficulties in maintaining such a time synchronization. In this paper, we implemented a system to synchronize clocks between FPGA based distributed embedded systems using the recovery clock of CDR (clock data recovery) used in high speed serial communication to solve the clock jitter error problem. It is experimentally confirmed that the cumulative time error that occurs when the synchronization is not performed through the synchronization logic using the CDR recovery clock can be completely eliminated.

• Journal of Electrical Engineering and Technology
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• 제7권3호
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• pp.429-435
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• 2012

In this study, a real-time architecture for the detection of clock jumps in the GPS clock behavior is proposed. GPS satellite atomic clocks have characteristics of a second order polynomial in the long term showing sudden jumps occasionally. As satellite clock anomalies influence on GPS measurements which could deliver wrong position information to users as a result, it is required to develop a real time technique for the detection of the clock anomalies especially on the real-time GPS applications such as aviation. The proposed strategy is based on Teager Energy operator, which can be immediately detect any changes in the satellite clock bias estimated from GPS carrier phase measurements. The verification results under numerous cases in the presence of clock jumps are demonstrated.

• Journal of Electrical Engineering and Technology
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• 제7권4호
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• pp.626-635
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• 2012

Most of single frequency GPS receivers utilize low-quality crystal oscillators. If a lowquality crystal oscillator is utilized as the time reference of a GPS receiver, the receiver's clock bias grows very fast due to its inherent low precision and poor stability. To prevent the clock bias becoming too large, large clock jumps are intentionally injected to the clock bias and the time offset for clock steering purpose. The abrupt changes in the clock bias and the time offset, if not properly considered, induce serious accuracy degradation in relative differential positioning. To prevent the accuracy degradation, this paper proposes an efficient and systematic method to eliminate the undesirable clock jump effects. Experiment results based on real measurements verify the effectiveness of the propose method.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.11-22
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• 2016

Clock skew scheduling is one of the essential steps to be carefully performed during the design process. This work addresses the clock skew optimization problem integrated with the consideration of the inter-dependent relation between the setup and hold times, and clock to-Q delay of flip-flops, so that the time margin is more accurately and reliably set aside over that of the previous methods, which have never taken the integrated problem into account. Precisely, based on an accurate flexible model of setup time, hold time, and clock-to-Q delay, we propose a stepwise clock skew scheduling technique in which at each iteration, the worst slack of setup and hold times is systematically and incrementally relaxed to maximally extend the time margin. The effectiveness of the proposed method is shown through experiments with benchmark circuits, demonstrating that our method relaxes the worst slack of circuits, so that the clock period ($T_{clk}$) is shortened by 4.2% on average, namely the clock speed is improved from 369 MHz~2.23 GHz to 385 MHz~2.33 GHz with no time violation. In addition, it reduces the total numbers of setup and hold time violations by 27.7%, 9.5%, and 6.7% when the clock periods are set to 95%, 90%, and 85% of the value of Tclk, respectively.

• 천문학논총
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• 제34권3호
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• pp.49-65
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• 2019

We investigate the provenance and the changes in the timekeeping system focusing on official records such as almanacs and textbooks published by the government after the solar calendar was introduced. We found that the solar calendar and the 12-hour clock time first appeared in 1884 during Joseon dynasty, at that time the solar calendar was used at the open port in Busan to facilitate the exchanges with Japan. The 12-hour clock time first appeared in the 『Hansung Sunbo』 published by the government in 1884. We also found that the Joseon dynasty also used 12 diǎnzhōng or 12 diǎn. In addition, the term of the 'Sigan' first appeared in the first official academic textbook in August 1895, and the chapter related to time contained the information about 12-hour clock time instead of the 12 Shi. In 1908, the meaning of the solar time, the equation of time, and the differences in longitude with the adoption of Korean Standard Time were introduced. Meanwhile, the 24-hour clock time was first introduced in Joseon and applied to railway times in 1907. The 1946 almanac, the first issue after liberation, used the 12-hour clock time which uses 'Sango', 'Hao' and the 24-hour clock time started to be used from the following year and is still used to this day. Finally, the 12-hour clock time, which was introduced around 1884, was enacted as Article 44 of the law in 1900 and was revised again in 1905 and 1908. In Korea, the terms related to the time in the current astronomical calendar system were newly defined around 1884, 1896, and 1908, and gradually standardized through the establishment of laws.

• 대한전자공학회논문지TC
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• 제42권6호
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• pp.17-22
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• 2005

동기방식 System에서는 모든 하위 Block에서 동일한 시간정보를 유지하는 것이 중요하다. 대부분의 기능들이 기준 Clock에 동기된 시간정보를 가지고 구현되므로 시간정보가 틀려지면 System에 치명적인 영향이 미치게 된다. 그러므로, 중요 Block에서는 이러한 시간정보/clock Signal의 정상 수신여부를 점검하는 부분이 꼭 필요하다. 본 논문에서는 Clock Signal을 점검하는 방법을 살펴보면서 발생할 수 있는 문제점에 대해 논하고 대안을 제시하고자 한다.

• International Journal of Advanced Culture Technology
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• 제4권4호
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• pp.30-37
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• 2016

In this paper, the method of controlling the clock that is inputted on the hardware from the application, and the hardware design method are to be proposed. When the hardware is synthesized to the Field Programmable Gate Array(FPGA), the input clock is fixed, and when the input clock is changed, the synthesis process must be passed again to require more time. To solve this problem, the Mixed-Mode Clock Manager(MMCM) module is mounted to control the MMCM module from the application. The controlled MMCM module controls the input clock of the module. The experiment was process the Neural Network algorithm in the x86 CPU and SIMT based processor mounted the FPGA. The results of the experiment, SIMT-based processors, the time that is processed at a frequency of 50MHz was 77ms, 100MHz was 34ms. There was no additional synthesis time due to a change of the clock frequency.

• 한국컴퓨터정보학회논문지
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• 제13권1호
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• pp.175-183
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• 2008

네트워크에서 QoS(quality of Service) 제공 기술은 양단간 네트워크 경로의 안정성과 성능의 정도를 나타내는 QoS 척도에 대한 실제 측정에 기반을 두고 있다. QoS 척도 중에서 특히 단방향 지연의 측정은 양단간 두 측정 지점간의 클럭(clock) 동기가 선행되어야 한다. 하지만, 네트워크에서 모든 단말 또는 호스트(host) 사이에는 절대적 또는 상대적인 시간 차이가 존재한다. 본 논문에서는, 단방향 지연 단방향 지연 변이와 일주 지연(round-trip time: RTT) 간의 관계식을 새롭게 유도하여 추정 오류가 일주지연의 사분의 일 이하가 됨을 수학적으로 보여주며, 이를 이용한 단방향 지연과 클럭 오프셋(offset)의 추정 기법을 제안하고 실험을 통하여 본 제안의 유용성을 보여준다.