• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.520-521
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• 2017

The converted error is occurred by the time difference between the time interval signal and the clock in a Time-to-Digital Converter of counter-type. If the clock period is $T_{CLOCK}$ the converted error is a maximum $T_{CLOCK}$ by the time difference between the start signal and the clock. And the converted error is a maximum $-T_{CLOCK}$ by the time difference between the stop signal and the clock. However, when the clock is synchronized with the start signal and the colck is generated during the time interval signal the range of converted digital error is from 0 to $(1/2)T_{CLOCK}$.

• Publications of The Korean Astronomical Society
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• v.28 no.2
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• pp.17-23
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• 2013

Song I-Yeong (1619 ~ 1692), who was an astronomy professor of Gwansanggam (觀象監, Bureau of Astronomy), created the Honcheonsigye (渾天時計, Armillary Clock) in 1669 (10th year of King Hyeonjong Era). Honcheonsigye was a unique astronomical clock which combined an armillary sphere, the traditional astronomical instrument of the Far East, with the power mechanism of western alarm clock. The clock part of this armillary clock is composed of two major parts which are the going-train, power unit used the weight, and the time signal system in a wooden case. The time signal system is composed of four parts which are the time-annunciator, the striking train, the 12 different time-announcing medallions and the sound bell. This clock has been neglected for many years and its several components have been lost. This study is to understand the structure of time signal system and suggests the restoration process.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.4
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• pp.239-246
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• 2017

Time synchronization between distributed embedded systems in the Real Time Locating System (RTLS) based on Time Difference of Arrival (TDOA) is one of the most important factors to consider in system design. Clock jitter error between each system causes many difficulties in maintaining such a time synchronization. In this paper, we implemented a system to synchronize clocks between FPGA based distributed embedded systems using the recovery clock of CDR (clock data recovery) used in high speed serial communication to solve the clock jitter error problem. It is experimentally confirmed that the cumulative time error that occurs when the synchronization is not performed through the synchronization logic using the CDR recovery clock can be completely eliminated.

• Journal of Electrical Engineering and Technology
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• v.7 no.3
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• pp.429-435
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• 2012

In this study, a real-time architecture for the detection of clock jumps in the GPS clock behavior is proposed. GPS satellite atomic clocks have characteristics of a second order polynomial in the long term showing sudden jumps occasionally. As satellite clock anomalies influence on GPS measurements which could deliver wrong position information to users as a result, it is required to develop a real time technique for the detection of the clock anomalies especially on the real-time GPS applications such as aviation. The proposed strategy is based on Teager Energy operator, which can be immediately detect any changes in the satellite clock bias estimated from GPS carrier phase measurements. The verification results under numerous cases in the presence of clock jumps are demonstrated.

• Journal of Electrical Engineering and Technology
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• v.7 no.4
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• pp.626-635
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• 2012

Most of single frequency GPS receivers utilize low-quality crystal oscillators. If a lowquality crystal oscillator is utilized as the time reference of a GPS receiver, the receiver's clock bias grows very fast due to its inherent low precision and poor stability. To prevent the clock bias becoming too large, large clock jumps are intentionally injected to the clock bias and the time offset for clock steering purpose. The abrupt changes in the clock bias and the time offset, if not properly considered, induce serious accuracy degradation in relative differential positioning. To prevent the accuracy degradation, this paper proposes an efficient and systematic method to eliminate the undesirable clock jump effects. Experiment results based on real measurements verify the effectiveness of the propose method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.11-22
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• 2016

Clock skew scheduling is one of the essential steps to be carefully performed during the design process. This work addresses the clock skew optimization problem integrated with the consideration of the inter-dependent relation between the setup and hold times, and clock to-Q delay of flip-flops, so that the time margin is more accurately and reliably set aside over that of the previous methods, which have never taken the integrated problem into account. Precisely, based on an accurate flexible model of setup time, hold time, and clock-to-Q delay, we propose a stepwise clock skew scheduling technique in which at each iteration, the worst slack of setup and hold times is systematically and incrementally relaxed to maximally extend the time margin. The effectiveness of the proposed method is shown through experiments with benchmark circuits, demonstrating that our method relaxes the worst slack of circuits, so that the clock period ($T_{clk}$) is shortened by 4.2% on average, namely the clock speed is improved from 369 MHz~2.23 GHz to 385 MHz~2.33 GHz with no time violation. In addition, it reduces the total numbers of setup and hold time violations by 27.7%, 9.5%, and 6.7% when the clock periods are set to 95%, 90%, and 85% of the value of Tclk, respectively.

• Publications of The Korean Astronomical Society
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• v.34 no.3
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• pp.49-65
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• 2019

We investigate the provenance and the changes in the timekeeping system focusing on official records such as almanacs and textbooks published by the government after the solar calendar was introduced. We found that the solar calendar and the 12-hour clock time first appeared in 1884 during Joseon dynasty, at that time the solar calendar was used at the open port in Busan to facilitate the exchanges with Japan. The 12-hour clock time first appeared in the 『Hansung Sunbo』 published by the government in 1884. We also found that the Joseon dynasty also used 12 diǎnzhōng or 12 diǎn. In addition, the term of the 'Sigan' first appeared in the first official academic textbook in August 1895, and the chapter related to time contained the information about 12-hour clock time instead of the 12 Shi. In 1908, the meaning of the solar time, the equation of time, and the differences in longitude with the adoption of Korean Standard Time were introduced. Meanwhile, the 24-hour clock time was first introduced in Joseon and applied to railway times in 1907. The 1946 almanac, the first issue after liberation, used the 12-hour clock time which uses 'Sango', 'Hao' and the 24-hour clock time started to be used from the following year and is still used to this day. Finally, the 12-hour clock time, which was introduced around 1884, was enacted as Article 44 of the law in 1900 and was revised again in 1905 and 1908. In Korea, the terms related to the time in the current astronomical calendar system were newly defined around 1884, 1896, and 1908, and gradually standardized through the establishment of laws.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.6 s.336
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• pp.17-22
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• 2005

It is important that we maintain the synchronous time-information with each other in the synchronous system. The most functions in the synchronous system need the time-information. n we have the wrong time-information, the system would operate incorrectly. So, we need to check if the time-information is correct or not in the important block of the synchronous system. In this paper, we will discuss how to check the clock signal and find some problem of it. Then, we will suggest the alternative plan.

• International Journal of Advanced Culture Technology
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• v.4 no.4
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• pp.30-37
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• 2016

In this paper, the method of controlling the clock that is inputted on the hardware from the application, and the hardware design method are to be proposed. When the hardware is synthesized to the Field Programmable Gate Array(FPGA), the input clock is fixed, and when the input clock is changed, the synthesis process must be passed again to require more time. To solve this problem, the Mixed-Mode Clock Manager(MMCM) module is mounted to control the MMCM module from the application. The controlled MMCM module controls the input clock of the module. The experiment was process the Neural Network algorithm in the x86 CPU and SIMT based processor mounted the FPGA. The results of the experiment, SIMT-based processors, the time that is processed at a frequency of 50MHz was 77ms, 100MHz was 34ms. There was no additional synthesis time due to a change of the clock frequency.

• Journal of the Korea Society of Computer and Information
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• v.13 no.1
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• pp.175-183
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• 2008

QoS-support technology in networks is based on measuring QoS metrics which reflect a magnitude of stability and performance. The one-way delay measurement of the QoS metrics especially requires a guarantee of clock synchronization between end-to-end hosts. However, the hosts in networks have a relative or absolute difference in clock time by reason of clock offsets. flock skews and clock adjustments. In this paper, we present a theorem, methods and simulation results of one-way delay and clock offset estimations between end-to-end hosts. The proposed theorem is a relationship between one-way delay, one-way delay variation and round-trip time And we show that the estimation error is mathematically smaller than a quarter of round-trip time.