• Title/Summary/Keyword: through-Si-via

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Wafer-level Vacuum Packaging of a MEMS Resonator using the Three-layer Bonding Technique (3중 접합 공정에 의한 MEMS 공진기의 웨이퍼레벨 진공 패키징)

  • Yang, Chung Mo;Kim, Hee Yeoun;Park, Jong Cheol;Na, Ye Eun;Kim, Tae Hyun;Noh, Kil Son;Sim, Gap Seop;Kim, Ki Hoon
    • Journal of Sensor Science and Technology
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    • v.29 no.5
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    • pp.354-359
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    • 2020
  • The high vacuum hermetic sealing technique ensures excellent performance of MEMS resonators. For the high vacuum hermetic sealing, the customization of anodic bonding equipment was conducted for the glass/Si/glass triple-stack anodic bonding process. Figure 1 presents the schematic of the MEMS resonator with triple-stack high-vacuum anodic bonding. The anodic bonding process for vacuum sealing was performed with the chamber pressure lower than 5 × 10-6 mbar, the piston pressure of 5 kN, and the applied voltage was 1 kV. The process temperature during anodic bonding was 400 ℃. To maintain the vacuum condition of the glass cavity, a getter material, such as a titanium thin film, was deposited. The getter materials was active at the 400 ℃ during the anodic bonding process. To read out the electrical signals from the Si resonator, a vertical feed-through was applied by using through glass via (TGV) which is formed by sandblasting technique of cap glass wafer. The aluminum electrodes was conformally deposited on the via-hole structure of cap glass. The TGV process provides reliable electrical interconnection between Si resonator and aluminum electrodes on the cap glass without leakage or electrical disconnection through the TGV. The fabricated MEMS resonator with proposed vacuum packaging using three-layer anodic bonding process has resonance frequency and quality factor of about 16 kHz and more than 40,000, respectively.

Study of CVD Growth Single-walled Carbon Nanotubes via Catalytic Layer Supported by Self-assembled Monolayer

  • Adhikari, Prashanta Dhoj;Kim, Sung-Hwan;Song, Woo-Seok;Lee, Su-Il;Park, Chong-Yun
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.08a
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    • pp.402-402
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    • 2012
  • Bundles of single-walled carbon nanotube (SWCNTs) were grown using catalytic layer supported by self-assembled monolayers (SAMs). Amine-SAMs were introduced on SiO2/Si substrate (SAMs/Si) there then iron nanoclusters solution was dropped on it through spin-coating (Fe/SAMs/Si). This catalytic template was used to grow CNTs and the synthesized carbon material was confirmed the bundles of dense SWCNTs with incorporation of ca.1% nitrogen. The SAMs has played an active role to support catalytic layer and also acted as a source of N-dope onto SWCNTs in CVD.

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Development of Two-Component Nanorod Complex for Dual-Fluorescence Imaging and siRNA Delivery

  • Choi, Jin-Ha;Oh, Byung-Keun
    • Journal of Microbiology and Biotechnology
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    • v.24 no.9
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    • pp.1291-1299
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    • 2014
  • Recently, multifunctional nanomaterials have been developed as nanotherapeutic agents for cellular imaging and targeted cancer treatment because of their ease of synthesis and low cytotoxicity. In this study, we developed a multifunctional, two-component nanorod consisting of gold (Au) and nickel (Ni) blocks that enables dual-fluorescence imaging and the targeted delivery of small interfering RNA (siRNA) to improve cancer treatment. Fluorescein isothiocyanate-labeled luteinizing hormone-releasing hormone (LHRH) peptides were attached to the surface of a Ni block via a histidine-tagged LHRH interaction to specifically bind to a breast cancer cell line, MCF-7. The Au block was modified with TAMRA-labeled thiolated siRNA in order to knock down the vascular endothelial growth factor protein to inhibit cancer growth. These two-component nanorods actively targeted and internalized into MCF-7 cells to induce apoptosis through RNA interference. This study demonstrates the feasibility of using two-component nanorods as a potential theranostic in breast cancer treatment, with capabilities in dual imaging and targeted gene delivery.

Ab Initio Study of Mechanism of Forming Spiro-Heterocyclic Ring Compound Involving Si and Ge from Dichlorosilylene Germylidene (Cl2Si-Ge:) and Acetone

  • Liu, Dongting;Ji, Hua;Lu, Xiuhui
    • Bulletin of the Korean Chemical Society
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    • v.33 no.12
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    • pp.4079-4083
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    • 2012
  • The mechanism of the cycloaddition reaction between singlet state dichlorosilylene germylidene ($Cl_2Si=Ge:$) and acetone has been investigated with B3LYP/6-$31G^*$ and B3LYP/6-$31G^{**}$ method, from the potential energy profile, we predict that the reaction has one dominant reaction pathway. The presented rule of the reaction is that the two reactants firstly form a Si-heterocyclic four-membered ring germylene through the [2+2] cycloaddition reaction. Because of the 4p unoccupied orbital of Ge atom in the Si-heterocyclic four-membered ring germylene and the ${\pi}$ orbital of acetone forming a ${\pi}{\rightarrow}p$ donor-acceptor bond, the Si-heterocyclic four-membered ring germylene further combines with acetone to form an intermediate. Because the Ge atom in the intermediate hybridizes to an $sp^3$ hybrid orbital after the transition state, then, the intermediate isomerizes to spiro-heterocyclic ring compound involving Si and Ge (P4) via a transition state.

The Development of an Electroconductive SiC-ZrB2 Ceramic Heater through Spark Plasma Sintering

  • Ju, Jin-Young;Kim, Cheol-Ho;Kim, Jae-Jin;Lee, Jung-Hoon;Lee, Hee-Seung;Shin, Yong-Deok
    • Journal of Electrical Engineering and Technology
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    • v.4 no.4
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    • pp.538-545
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    • 2009
  • The SiC-$ZrB_2$ composites were fabricated by combining 30, 35, 40 and 45vol.% of Zirconium Diboride (hereafter, $ZrB_2$) powders with Silicon Carbide (hereafter, SiC) matrix. The SiC-$ZrB_2$ composites, the sintered compacts, were produced through Spark Plasma Sintering (hereafter, SPS), and its physical, electrical, and mechanical properties were examined. Also, the thermal image analysis of the SiC-$ZrB_2$ composites was examined. Reactions between $\beta$-SiC and $ZrB_2$ were not observed via X-Ray Diffractometer (hereafter, XRD) analysis. The relative density of the SiC+30vol.%$ZrB_2$, SiC+35vol.%$ZrB_2$, SiC+40vol.%$ZrB_2$, and SiC+45vol.%$ZrB_2$ composites were 88.64%, 76.80%, 79.09% and 88.12%, respectively. The XRD phase analysis of the sintered compacts demonstrated high phase of SiC and $ZrB_2$ but low phase of $ZrO_2$. Among the SiC-$ZrB_2$ composites, the SiC+35vol.%$ZrB_2$ composite had the lowest flexural strength, 148.49MPa, and the SiC+40vol.%$ZrB_2$ composite had the highest flexural strength, 204.85MPa, at room temperature. The electrical resistivities of the SiC+30vol.%$ZrB_2$, SiC+35vol.%$ZrB_2$, SiC+40vol.%$ZrB_2$ and SiC+45vol.%$ZrB_2$ composites were $6.74\times10^{-4}$, $4.56\times10^{-3}$, $1.92\times10^{-3}$, and $4.95\times10^{-3}\Omega{\cdot}cm$ at room temperature, respectively. The electrical resistivities of the SiC+30vol.%$ZrB_2$, SiC+35vol.%$ZrB_2$ SiC+40vol.%$ZrB_2$ and SiC+45[vol.%]$ZrB_2$ composites had Positive Temperature Coefficient Resistance (hereafter, PTCR) in the temperature range from $25^{\circ}C$ to $500^{\circ}C$. The V-I characteristics of the SiC+40vol.%$ZrB_2$ composite had a linear shape. Therefore, it is considered that the SiC+40vol.%$ZrB_2$ composite containing the most outstanding mechanical properties, high resistance temperature coefficient and PTCR characteristics among the sintered compacts can be used as an energy friendly ceramic heater or electrode material through SPS.

Cu-Filling Behavior in TSV with Positions in Wafer Level (Wafer 레벨에서의 위치에 따른 TSV의 Cu 충전거동)

  • Lee, Soon-Jae;Jang, Young-Joo;Lee, Jun-Hyeong;Jung, Jae-Pil
    • Journal of the Microelectronics and Packaging Society
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    • v.21 no.4
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    • pp.91-96
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    • 2014
  • Through silicon via (TSV) technology is to form a via hole in a silicon chip, and to stack the chips vertically for three-dimensional (3D) electronics packaging technology. This can reduce current path, power consumption and response time. In this study, Cu-filling substrate size was changed from Si-chip to a 4" wafer to investigate the behavior of Cu filling in wafer level. The electrolyte for Cu filling consisted of $CuSO_4$ $5H_2O$, $H_2SO_4$ and small amount of additives. The anode was Pt, and cathode was changed from $0.5{\times}0.5cm^2$ to 4" wafer. As experimental results, in the case of $5{\times}5cm^2$ Si chip, suitable distance of electrodes was 4cm having 100% filling ratio. The distance of 0~0.5 cm from current supplying location showed 100% filling ratio, and distance of 4.5~5 cm showed 95%. It was confirmed good TSV filling was achieved by plating for 2.5 hrs.

Characterization of Backside Passivation Process for Through Silicon via Wafer (TSV 웨이퍼 공정용 Si3N4 후막 스트레스에 대한 공정특성 분석)

  • Kang, Dong Hyun;Gu, Jung Mo;Ko, Young-Don;Hong, Sang Jeen
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.27 no.3
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    • pp.137-140
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    • 2014
  • With the recent advent of through silicon via (TSV) technology, wafer level-TSV interconnection become feasible in high volume manufacturing. To increase the manufacturing productivity, it is required to develop equipment for backside passivation layer deposition for TSV wafer bonding process with high deposition rate and low film stress. In this research, we investigated the relationship between process parameters and the induced wafer stress of PECVD silicon nitride film on 300 mm wafers employing statistical and artificial intelligence modeling. We found that the film stress increases with increased RF power, but the pressure has inversely proportional to the stress. It is also observed that no significant stress change is observed when the gas flow rate is low.

Thermal stress intensity factor solutions for reactor pressure vessel nozzles

  • Jeong, Si-Hwa;Chung, Kyung-Seok;Ma, Wan-Jun;Yang, Jun-Seog;Choi, Jae-Boong;Kim, Moon Ki
    • Nuclear Engineering and Technology
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    • v.54 no.6
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    • pp.2188-2197
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    • 2022
  • To ensure the safety margin of a reactor pressure vessel (RPV) under normal operating conditions, it is regulated through the pressure-temperature (P-T) limit curve. The stress intensity factor (SIF) obtained by the internal pressure and thermal load should be obtained through crack analysis of the nozzle corner crack in advance to generate the P-T limit curve for the nozzle. In the ASME code Section XI, Appendix G, the SIF via the internal pressure for the nozzle corner crack is expressed as a function of the cooling or heating rate, and the wall thickness, however, the SIF via the thermal load is presented as a polynomial format based on the stress linearization analysis results. Inevitably, the SIF can only be obtained through finite element (FE) analysis. In this paper, simple prediction equations of the SIF via the thermal load under, cool-down and heat-up conditions are presented. For the Korean standard nuclear power plant, three geometric variables were set and 72 cases of RPV models were made, and then the heat transfer analysis and thermal stress analysis were performed sequentially. Based on the FE results, simple engineering solutions predicting the value of thermal SIF under cool-down and heat-up conditions are suggested.

Relation between Resistance and Capacitance in Atomically Dispersed Pt-SiO2 Thin Films for Multilevel Resistance Switching Memory (Pt 나노입자가 분산된 SiO2 박막의 저항-정전용량 관계)

  • Choi, Byung Joon
    • Korean Journal of Materials Research
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    • v.25 no.9
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    • pp.429-434
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    • 2015
  • Resistance switching memory cells were fabricated using atomically dispersed Pt-$SiO_2$ thin film prepared via RF co-sputtering. The memory cell can switch between a low-resistance-state and a high-resistance-state reversibly and reproducibly through applying alternate voltage polarities. Percolated conducting paths are the origin of the low-resistance-state, while trapping electrons in the negative U-center in the Pt-$SiO_2$ interface cause the high-resistance-state. Intermediate resistance-states are obtained through controlling the compliance current, which can be applied to multi-level operation for high memory density. It is found that the resistance value is related to the capacitance of the memory cell: a 265-fold increase in resistance induces a 2.68-fold increase in capacitance. The exponential growth model of the conducting paths can explain the quantitative relationship of resistance-capacitance. The model states that the conducting path generated in the early stage requires a larger area than that generated in the last stage, which results in a larger decrease in the capacitance.

Interconnection Process and Electrical Properties of the Interconnection Joints for 3D Stack Package with $75{\mu}m$ Cu Via ($75{\mu}m$ Cu via가 형성된 3D 스택 패키지용 interconnection 공정 및 접합부의 전기적 특성)

  • Lee Kwang-Yong;Oh Teck-Su;Won Hye-Jin;Lee Jae-Ho;Oh Tae-Sung
    • Journal of the Microelectronics and Packaging Society
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    • v.12 no.2 s.35
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    • pp.111-119
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    • 2005
  • Stack specimen with three dimensional interconnection structure through Cu via of $75{\mu}m$ diameter, $90{\mu}m$ height and $150{\mu}m$ pitch was successfully fabricated using subsequent processes of via hole formation with Deep RIE (reactive ion etching), Cu via filling with pulse-reverse electroplating, Si thinning with CMP, photolithography, metal film sputtering, Cu/Sn bump formation, and flip chip bonding. Contact resistance of Cu/Sn bump and Cu via resistance could be determined ken the slope of the daisy chain resistance vs the number of bump joints of the flip chip specimen containing Cu via. When flip- chip bonded at $270^{\circ}C$ for 2 minutes, the contact resistance of the Cu/Sn bump joints of $100{\times}100{\mu}m$ size was 6.7m$\Omega$ and the Cu via resistance of $75{\mu}m$ diameter, $90{\mu}m$ height was 2.3m$\Omega$.

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