• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.595-596
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• 2006

A novel Si via structure is suggested and fabricated for 3D MEMS package using the doped silicon as an interconnection material. Oxide isolations which define Si via are formed simultaneously when fabricating the MEMS structure by using DRIE and oxidation. Silicon Direct Bonding Multi-stacking process is used for stacked package, which consists of a substrate, MEMS structure layer and a cover layer. The bonded wafers are thinned by lapping and polishing. A via with the size of $20{\mu}m$ is fabricated and the electrical and mechanical characteristics of via are under testing.

• Korean Chemical Engineering Research
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• v.54 no.6
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• pp.723-733
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• 2016

Intensive researches have been focused on the 3-dimensional packaging technology using through silicon via (TSV) to overcome the limitation in Cu interconnection scaling. Void-free filling of TSV by the Cu electrodeposition is required for the fabrication of reliable electronic devices. It is generally known that sufficient inhibition on the top and the sidewall of TSV, accompanying the selective Cu deposition on the bottom, enables the void-free bottom-up filling. Organic additives contained in the electrolyte locally determine the deposition rate of Cu inside the TSV. Investigation on the additive chemistry is essential for understanding the filling mechanisms of TSV based on the effects of additives in the Cu electrodeposition process. In this review, we introduce various filling mechanisms suggested by analyzing the additives effect, research on the three-additive system containing new levelers synthesized to increase efficiency of the filling process, and methods to improve the filling performance by modifying the functional groups of the additives or deposition mode.

• Asian Pacific Journal of Cancer Prevention
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• v.17 no.9
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• pp.4313-4318
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• 2016

Background: This study documented the performance of providers of visual inspection with acetic acid (VIA) at primary health centers, assessing their compliance with the VIA skills checklist and determinants of non-compliance, and exploring their perceptions of VIA training sessions. Materials and Methods: A cross-sectional study was conducted among VIA providers in the $Mekn\grave{e}s$-Tafilalet region of Morocco. Structured observation of their performance was conducted through supervisory visits and multiple focus group discussions (FGDs). Results: Performance of all the recommended steps for effective communication was observed in a low proportion of procedures (36.4%). Midwives/nurses had higher compliance than general practitioners (GPs) (p<0.001). All recommended steps for VIA examination were performed for a high proportion of procedures (82.5%). Compliance was higher among midwives/nurses than among GPs (p<0.001) and among providers in rural areas than those in urban areas (p<0.001). For pre-VIA counselling, all recommended steps were performed for only 36.8% of procedures. For post-VIA counseling, all recommended steps were performed in a high proportion (85.5% for VIA-negative and 85.1% for VIA-positive women). Midwives/nurses had higher compliance than GPs when advising VIA-positive women (p=0.009). All infection prevention practices were followed for only 14.2% of procedures, and compliance was higher among providers in rural areas than those in urban areas (p<0.001). Most FGD participants were satisfied with the content of VIA training sessions. However, they suggested periodic refresher training and supportive supervision. Conclusions: Quality assurance of a cervical cancer screening program is a key element to ensure that the providers perform VIA correctly and confidently.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.10
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• pp.539-549
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• 2002

PC cluster-based Information Retrieval (IR) systems improve their performances by parallel processing of query terms using cluster nodes. However TCP/IP based communication used to exchange data between cluster nodes prevents the performance from being improved further. The user-level communication mechanisms solve the problem by eliminating the time-consuming kernel access in exchanging data between cluster nodes. The Virtual Interface Architecture (VIA) is one of the representative user-level communication mechanisms which provide low latency and high bandwidth. In this paper, we propose a VIA-based parallel IR system on a PC cluster. The IR system is implemented using the following three communication methods: Sealable Coherent Interface (SCI) based VIA, MPI on SCI based VIA, MPI on Fast Ethernet based VIA. Through experiments, the performances of the three methods are analyzed in various aspects.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.217-221
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• 2004

[ $CO_2$ ]laser ablation rates for bulk 4H-SiC substrates and GaN/AIN/SiC templates in the range 229-870 ${\mu}m.min^{-1}$ were obtained for pulse energies of 7.5-30 mJ over diameters of 50·500 ${\mu}m$ with a Q-switched pulse width of ${\sim}30$ nsec and a pulse frequency of 8 Hz. The laser drilling produces much higher etch rates than conventional dry plasma etching (0.2 - 1.3 ${\mu}m/min$) making this an attractive maskless option for creating through-wafer via holes in SiC or GaN/AlN/SiC templates for power metal-semiconductor field effect transistor applications. The via entry can be tapered to facilitate subsequent metallization by control of the laser power and the total residual surface contamination can be minimized in a similar fashion and with a high gas throughput to avoid redeposition. The sidewall roughness is also comparable or better than conventional via holes created by plasma etching.

• ETRI Journal
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• v.35 no.4
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• pp.571-577
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• 2013

The fabrication of a thin-film transistor backplane and a liquid-crystal display using printing processes can eliminate the need for photolithography and offers the potential to reduce the manufacturing costs. In this study, we prepare contact via structures through a poly(methyl methacrylate) polymer insulator layer using inkjet printing. When droplets of silver ink composed of a polymer solvent are placed onto the polymer insulator and annealed at high temperatures, the silver ink penetrates the interior of the polymer and generates conducting paths between the top and bottom metal lines through the partial dissolution and swelling of the polymer. The electrical property of various contact via-hole interconnections is investigated using a semiconductor characterization system.

• Journal of Welding and Joining
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• v.29 no.1
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• pp.46-51
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• 2011

TSV technology raises several reliability concerns particularly caused by thermally induced stress. In traditional package, the thermo-mechanical failure mostly occurs as a result of the damage in the solder joint. In TSV technology, however, the driving failure may be TSV interconnects. In this study, the thermomechanical reliability of TSV technology is investigated using finite element method. Thermal stress and thermal fatigue phenomenon caused by repetitive temperature cycling are analyzed, and possible failure locations are discussed. In particular, the effects of via size, via pitch and bonding pad on thermo-mechanical reliability are investigated. The plastic strain generally increases with via size increases. Therefore, expected thermal fatigue life also increase as the via size decreases. However, the small via shows the higher von Mises stress. This means that smaller vias are not always safe despite their longer life expectancy. Therefore careful design consideration of via size and pitch is required for reliability improvement. Also the bonding pad design is important for enhancing the reliability of TSV structure.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12S
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• pp.1237-1241
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• 2003

In this paper, we report a novel RF-MEMS packaging technology with lightweight, small size, and short electric path length. To achieve this goal, we used the ultra thin silicon substrate as a packaging substrate. The via holes lot vortical feed-through were fabricated on the thin silicon wafer by wet chemical processing. Then, via holes were filled and micro-bumps were fabricated by electroplating. The packaged RF device has a reflection loss under 22 〔㏈〕 and a insertion loss of -0.04∼-0.08 〔㏈〕. These measurements show that we could package the RF device without loss and interference by using the vertical feed-through. Specially, with the ultra thin silicon wafer we can realize of a device package that has low-cost, lightweight and small size. Also, we can extend a 3-D packaging structure by stacking assembled thin packages.

• Convergence Security Journal
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• v.18 no.1
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• pp.93-102
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• 2018

The drug trade among the general public via the Internet and sns have been increasing, which is becoming a social problem. The general public believe that even if they do the drug trade via the Internet and sns the probability of detection is low. so they will conduct drug trade via the Internet and sns. Therefore, if the general public recognize that there is a high likelihood of disclosure, drug trade via the Internet and sns are likely to decline. If the possibility of punishment increases through specification of controlled delivery techniques and Introduction of entrapment investigator, it seems that the general public can not easily deal with drug trade via the Internet and sns. Also by further subdividing the penalties for drug offenses, for simple drug buyers through cure-oriented treatment rather than punishment drug demand be suppressed and penalties for drug suppliers should be strengthened.

• Korean Journal of Metals and Materials
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• v.49 no.5
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• pp.388-394
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• 2011

High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37${\mu}m$ at the via opening, and 32${\mu}m$ at the via bottom, respectively and a depth of 70${\mu}m$. $SiO_2$, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was filled to 100% at -5.85 mA/$cm^2$ for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to fill the TSV in a short time.