• Title/Summary/Keyword: threshold voltage variation

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Comparative Analysis of PBTI Induced Device Degradation in Junctionless and Inversion Mode Multiple-Gate MOSFET (PBTI에 의한 무접합 및 반전모드 다중게이트 MOSFET의 소자 특성 저하 비교 분석)

  • Kim, Jin-Su;Hong, Jin-Woo;Kim, Hye-Mi;Lee, Jae-Ki;Park, Jong-Tae
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.1
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    • pp.151-157
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    • 2013
  • In this paper, a comparative analysis of PBTI induced device degradation in nanowire n-channel junctionless and inversion mode Multiple-Gate MOSFET(MuGFETs) has been performed. It has been observed that the threshold voltage is increased after PBTI stress and the threshold voltage variation of junctionless device is less significant than that of inversion mode device. However the degradation rate of junctionless device is less significant than that of inversion mode device. The activation energy of the device degradation is larger in inversion mode device than junctionless device. In order to analyze the more significant PBTI induced device degradation in inversion mode device than junctionless device, 3-dimensional device simulation has been performed. The electron concentration in inversion mode device is equal to the one in junctionless device but the electric field in inversion mode device is larger than junctionless device.

Low voltage operating $InGaZnO_4$ thin film transistors using high-k $MgO_{0.3}BST_{0.7}$ gate dielectric (고유전 $MgO_{0.3}BST_{0.7}$ 게이트 절연막을 이용한 $InGaZnO_4$ 기반의 트랜지스터의 저전압 구동 특성 연구)

  • Kim, Dong-Hun;Cho, Nam-Gyu;Chang, Young-Eun;Kim, Ho-Gi;Kim, Il-Doo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.40-40
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    • 2008
  • $InGaZnO_4$ based thin film transistors (TFTs) are of interest for large area and low cost electronics. The TFTs have strong potential for application in flat panel displays and portable electronics due to their high field effect mobility, high on/off current ratios, and high optical transparency. The application of such room temperature processed transistors, however, is often limited by the operation voltage and long-tenn stability. Therefore, attaining an optimum thickness is necessary. We investigated the thickness dependence of a room temperature grown $MgO_{0.3}BST_{0.7}$ composite gate dielectric and an $InGaZnO_4$ (IGZO) active semiconductor on the electrical characteristics of thin film transistors fabricated on a polyethylene terephthalate (PET) substrate. The TFT characteristics were changed markedly with variation of the gate dielectric and semiconductor thickness. The optimum gate dielectric and active semiconductor thickness were 300 nm and 30 nm, respectively. The TFT showed low operating voltage of less than 4 V, field effect mobility of 21.34 cm2/$V{\cdot}s$, an on/off ratio of $8.27\times10^6$, threshold voltage of 2.2 V, and a subthreshold swing of 0.42 V/dec.

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Current-Voltage Characteristics of Schottky Barrier SOI nMOS and pMOS at Elevated Temperature (고온에서 Schottky Barier SOI nMOS 및 pMOS의 전류-전압 특성)

  • Ka, Dae-Hyun;Cho, Won-Ju;Yu, Chong-Gun;Park, Jong-Tae
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.4
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    • pp.21-27
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    • 2009
  • In this work, Er-silicided SB-SOI nMOSFET and Pt-silicided SB-SOI pMOSFET have been fabricated to investigate the current-voltage characteristics of Schottky barrier SOI nMOS and pMOS at elevated temperature. The dominant current transport mechanism of SB nMOS and pMOS is discussed using the measurement results of the temperature dependence of drain current with gate voltages. It is observed that the drain current increases with the increase of operating temperature at low gate voltage due to the increase of thermal emission and tunneling current. But the drain current is decreased at high gate voltage due to the decrease of the drift current. It is observed that the ON/Off current ratio is decreased due to the increased tunneling current from the drain to channel region although the ON current is increased at elevated temperature. The threshold voltage variation with temperature is smaller and the subthreshold swing is larger in SB-SOI nMOS and pMOS than in SOI devices or in bulk MOSFETs.

An Improved Gate Control Scheme for Overvoltage Clamping Under High Power IGBTs Switching (대용량 IGBT 스위칭 시 과전압 제한을 위한 향상된 게이트 구동기법)

  • 김완중;최창호;이요한;현동석
    • The Transactions of the Korean Institute of Power Electronics
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    • v.3 no.3
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    • pp.222-230
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    • 1998
  • This paper proposes a new gate drive circuit for high power IGBTs which can reduce the harmful effect of reverse recovery current at turn-on and actively suppress the overvoltage across the driven IGBT at turn-off without a snubber circuit. The turn-on scheme decreases the rising rate of the collector current by inereasing the input capacitance at turn-on transient when the gate-emitter voltage goes above threshold voltage. It results in soft transient of the reverse recovery current with no variation in turn-on delay time. The turn-off driving scheme has adaptive feature to the amplitude of collector current, so that the overvoltage can be limited much effectively at the fault collector current. Experimental results under various normal and fault conditions prove the effectiveness of the proposed circuit.

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Potential Distribution Model for FinFET using Three Dimensional Poisson's Equation (3차원 포아송방정식을 이용한 FinFET의 포텐셜분포 모델)

  • Jung, Hak-Kee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.13 no.4
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    • pp.747-752
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    • 2009
  • Three dimensional(3D) Poisson's equation is used to calculate the potential variation for FinFET in the channel to analyze subthreshold current and short channel effect(SCE). The analytical model has been presented to lessen calculating time and understand the relationship of parameters. The accuracy of this model has been verified by the data from 3D numerical device simulator and variation for dimension parameters has been explained. The model has been developed to obtain channel potential of FinFET according to channel doping and to calculate subthreshold current and threshold voltage.

3차원 포아송방정식을 이용한 FinFET의 해석학적 포텐셜모델

  • Han, Ji-Hyung;Jung, Hak-Kee;Jung, Dong-Soo;Lee, Jong-In;Kwon, Oh-Shin
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2008.10a
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    • pp.579-582
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    • 2008
  • Three dimensional(3D) Poisson's equation is used to calculate the potential variation in the channel to analyze subthreshold current and short channel effect(SCE). The analytical model has been presented to lessen calculating time and understand the relationship of parameters. The accuracy of this model has been verified by the data from 3D numerical device simulator and variation for dimension and process parameters has been explained. The model has been developed to obtain channel potential of FinFET according to channel doping and to calculate subthreshold current and threshold voltage.

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Grain distribution and electrical property according to grain size variation in polysilicon TFTs (다결정 실리콘 TFT소자의 채널길이 변화에 따른 grain의 분포와 전기적 특성)

  • Lee, Eun-Nyung;Song, Ho-Young;Park, Se-Geun;Lee, Taek-Joo;O, Beom-Hoan;Lee, Seung-Gol;Lee, El-Hang
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.11a
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    • pp.128-131
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    • 2003
  • The number of grain is determined based on Poisson distribution in respectively different active channel and it is converted to grain size which affects to the mobility and threshold voltage. the acquired data is applied to the SPICE for observing the variation of I-V characteristic with several channel lengths. we can confirm the effect on device.

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Thermal treatments effects on the properties of zinc tin oxide transparent thin film transistors (Zinc tin oxide 투명박막트랜지스터의 특성에 미치는 열처리 효과)

  • Ma, Tae Young
    • Journal of IKEEE
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    • v.23 no.2
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    • pp.375-379
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    • 2019
  • $ZnO-SnO_2(ZTO)$ was deposited by RF magnetron sputtering using a ceramic target whose Zn atomic ratio to Sn is 2:1 as a target, and the crystal structure variation with thermal treats was investigated. Transparent thin film transistors (TTFT) were fabricated using the ZTO films as active layers. About 100 nm-thick $Si_3N_4$ film grown on 100 nm-thick $SiO_2$ film was adopted as gate dielectrics. The mobility, threshold voltage, $I_{on}/I_{off}$, and interface trap density were obtained from the transfer characteristics of ZTO TTFTs. The effects of substrate temperature, and post-annealing on the property variation of ZTO TTFT were analyzed.

Study on die electric characteristics of TIPS-pentacene transistors with variation of electrode thickness (소스/드레인 전극의 두께변화에 따른 TIPS-pentacene 트랜지스터의 전기적 특성 연구)

  • Yang, Jin-Woo;Hyung, Gun-Woo;Kim, Young-Kwan
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.06a
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    • pp.323-324
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    • 2009
  • We investigated the electrical properties of tris-isopropylsilylethynyl (TIPS)-pentacene organic thin-film transistors (OTFTs) employing Ni/Ag source/drain electrodes. The gap height between the gate insulator and S/D electrode was controlled by changing the thickness of Ag under-layer(20, 30, 40 and 50nm). After evaporating the Ni under-layer, TIPS pentacene channel material was dropping the gap between the gate insulator and SID electrodes. The electrical proprieties of OTFT such as filed-effect mobility, on/off ratio, threshold voltage and subthreshold slope were significantly influenced by the gap height.

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Drain-current Modeling of Sub-70-nm PMOSFETs Dependent on Hot-carrier Stress Bias Conditions

  • Lim, In Eui;Jhon, Heesauk;Yoon, Gyuhan;Choi, Woo Young
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.1
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    • pp.94-100
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    • 2017
  • Stress drain bias dependent current model is proposed for sub-70-nm p-channel metal-oxide semiconductor field-effect transistors (pMOSFETs) under drain-avalanche-hot-carrier (DAHC-) mechanism. The proposed model describes the both on-current and off-current degradation by using two device parameters: channel length variation (${\Delta}L_{ch}$) and threshold voltage shift (${\Delta}V_{th}$). Also, it is a simple and effective model of predicting reliable circuit operation and standby power consumption.