• Transactions on Electrical and Electronic Materials
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• v.18 no.1
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• pp.51-54
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• 2017

TFTs (thin film transistors) were fabricated using a-SIZO (amorphous silicon-indium-zinc-oxide) channel by RF (radio frequency) magnetron sputtering at room temperature. We report the influence of various channel thickness on the electrical performances of a-SIZO TFTs and their stability, using TS (temperature stress) and NBTS (negative bias temperature stress). Channel thickness was controlled by changing the deposition time. As the channel thickness increased, the threshold voltage ($V_{TH}$) of a-SIZO changed to the negative direction, from 1.3 to -2.4 V. This is mainly due to the increase of carrier concentration. During TS and NBTS, the threshold voltage shift (${\Delta}V_{TH}$) increased steadily, with increasing channel thickness. These results can be explained by the total trap density ($N_T$) increase due to the increase of bulk trap density ($N_{Bulk}$) in a-SIZO channel layer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.8
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• pp.637-640
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• 2009

In this work, we demonstrate 800 V 4H-SiC power DMOSFETs with several structural alterations to obtain a low threshold voltage ($V_{TH}$) and a high figure of merit ($V_B\;^2/R_{SP,ON}$), To optimize the device performance, we consider four design parameters; (a) the doping concentration ($N_{CSL}$) of current spreading layer (CSL) beneath the p-base region, (b) the thickness of p-base ($t_{BASE}$), (c) the doping concentration ($N_J$) and width ($W_J$) of a JFET region, (d) the doping concentration ($N_{EPI}$) and thickness ($t_{EPI}$) of epi-layer. These parameters are optimized using 2D numerical simulation and the 4H-SiC DMOSFET structure results in a threshold voltage ($V_{TH}$) below $^{\sim}$3.8 V, and high figure of merit ($V_B\;^2/R_{SP,ON}$>$^{\sim}$200 $MW/cm^2$) for a power MOSFET in $V_B\;^{\sim}$800 V range.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.8-8
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• 2009

Thin-film transistors (TFTs) were fabricated using amorphous indium gallium zinc oxide (a-IGZO) channels by rf-magnetron sputtering at room temperature. We have studied the effect of oxygen partial pressure on the threshold voltage($V_{th}$) of a-IGZO TFTs. Interestingly, the $V_{th}$ value of the oxide TFTs are slightly shifted in the positive direction due to increasing $O_2$ ratio from 1.2 to 1.8%. The device performance is significantly affected by varying $O_2$ ratio, which is closely related with oxygen vacancies provide the needed free carriers for electrical conduction.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.4
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• pp.275-277
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• 2013

Thin-film transistors(TFTs) with silicon zinc tin oxide(SZTO) channel layer are fabricated by solution-process. The threshold voltage ($V_{th}$) shifted toward positive directly with increasing Si contents in SZTO system. Because the Si has a lower standard electrode potential (SEP) than Sn, Zn, thus degenerate the oxygen vacancy (VO). As a result, the Si act as carrier suppressor and oxygen binder in the SZTO as well as a $V_{th}$ controller.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.9
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• pp.677-680
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• 2012

The dependency of annealing temperature on the electrical performances in amorphous silicon-zinc-tin-oxide thin film transistors (SZTO-TFT) has been investigated. The SZTO channel layers were prepared by using radio frequency (RF) magnetron sputtering method with different annealing treatment. The field effect mobility (${\mu}_{FE}$) increased and threshold voltage ($V_{th}$) shifted to negative direction with increasing annealing temperature. As a result, oxygen vacancies generated in SZTO channel layer with increasing annealing temperature resulted in negative shift in $V_{th}$ and increase in on-current.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.8
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• pp.580-583
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• 2012

The dependency of processing pressure on the electrical performances in amorphous silicon-zinc-tin-oxide thin film transistors (SZTO-TFT) has been investigated. The SZTO channel layers were deposited by using radio frequency (RF) magnetron sputtering method with different partial pressure. The field effect mobility (${\mu}_{FE}$) increased and threshold voltage ($V_{th}$) shifted to negative direction with increasing pressure during deposition processing. As a result, oxygen vacancies generated in SZTO channel layer with increasing partial pressure resulted in negative shift in $V_{th}$ and increase in on-current.

• Transactions on Electrical and Electronic Materials
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• v.15 no.6
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• pp.315-319
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• 2014

In this paper, we investigate visible light stress instability in radio frequency (RF) sputtered a-IGZO thin film transistors (TFTs). The oxygen flow rate differs during deposition to control the concentration of oxygen vacancies, which is confirmed via RT PL. A negative shift is observed in the threshold voltage ($V_{TH}$) under illumination with/without the gate bias, and the amount of shift in $V_{TH}$ is proportional to the concentration of oxygen vacancies. This can be explained to be consistent with the ionization oxygen vacancy model where the instability in $V_{TH}$ under illumination is caused by the increase in the channel conductivity by electrons that are photo-generated from oxygen vacancies, and it is maintained after the illumination is removed due to the negative-U center properties.

• Current Applied Physics
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• v.18 no.11
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• pp.1447-1450
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• 2018

The electron spin resonance (ESR) detects point defect of the In-Ga-Zn oxide (IGZO) like singly ionized oxygen vacancies and excess oxygen, and get spin density as a parameter of defect state. So, we demonstrated the spin density measurement of the IGZO film with various deposition conditions and it has linear relationship. Moreover, we matched the spin density with the total BTS and the threshold voltage ($V_{th}$) distribution of the IGZO thin film transistors. The total BTS ${\Delta}V_{th}$ and the $V_{th}$ distribution were degraded due to the spin density increases. The spin density is the useful indicator to predict $V_{th}$ instability of IGZO TFTs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.8
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• pp.575-581
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• 2013

The self-cascode (SC) structure has low output voltage swing and high output resistance. In order to implement a simple and better SC structure, the native-$V_{th}$ MOSFETs which has low threshold voltage($V_{th}$) is applied. The proposed SC structure is designed using a qualified industry standard $0.18-{\mu}m$ CMOS technology. Measurement results show that the proposed SC structure has higher transconductance as well as output resistance than single MOSFET. In addition, analog building blocks (e.g. current mirror, basic amplifier circuits) with the proposed SC structure are investigated using by Cadence Spectre simulator. Simulation results show improved electrical performances.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.911-913
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• 2008

In this work, nonvolatile memory (NVM) devices for system on panel of flat panel display (FPD) were fabricated using low temperature polycrystalline silicon (LTPS) thin film transistor (TFT) technology with an oxide-nitride-oxynitride (ONOn) stack structure on glass. The results demonstrate that the NVM devices fabricated using the ONOn stack structure on glass have suitable switching characteristics for data storage with a low operating voltage, a threshold voltage window of more than 1.8 V between the programming and erasing (P/E) states after 10 years and its initial threshold voltage window (${\Delta}V_{TH}$) after $10^5$ P/E cycles.