• IEIE Transactions on Smart Processing and Computing
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• v.3 no.5
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• pp.331-337
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• 2014

Ge is becoming an increasingly popular semiconductor material with high Si compatibility for on-chip optical interconnect technology. For a better manifestation of the meritorious material properties of Ge, its surface treatment should be performed satisfactorily before the electronic and photonic components are fabricated. Ex-situ rapid thermal annealing (RTA) processes with different gases were carried out to examine the effects of the annealing gases on the thin-film quality of Ge grown epitaxially on Si substrates. The Ge-on-Si samples were prepared in different structures using the same equipment, reduced-pressure chemical vapor deposition (RPCVD), and the samples annealed in $N_2$, forming gas (FG), and $O_2$ were compared with the unannealed (deposited and only cleaned) samples to confirm the improvements in Ge quality. To evaluate the thin-film quality, room-temperature photoluminescence (PL) measurements were performed. Among the compared samples, the $O_2$-annealed samples showed the strongest PL signals, regardless of the sample structures, which shows that ex-situ RTA in the $O_2$ environment would be an effective technique for the surface treatment of Ge in fabricating Ge devices for optical computing systems.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.652-652
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• 2013

The conventional thermal chemical vapor deposition (CVD) setup for the graphene synthesis has mainly used convective heat transfer in order to heat a catalyst (e.g. Cu) up to $1,000^{\circ}C$. Although the conventional CVD has been so far widely accepted as the most appropriate candidate enabling mass-production of high-quality graphene, this method has stillremained under the standard for the commercialization largely due to the poor productivity arisen out of the required long processing time. Here, we introduced a fast and efficient synthetic route toward CVD-graphene. Unlike the conventional CVD using convection heat transfer, we adopted a CVD setup utilizing conduction heat transfer between Cu catalyst and rapid heating source. The high thermal conductive nature of Cu and the employed rapid heating source led to the remarkable reduction in processing timeas compared to the conventional convection based CVD (Fig. 1A), moreover, the synthesized graphene was turned out to have comparable quality to that synthesized by the conventional CVD (Fig. 1B). For the optimization of the conduction based CVD process, the parametric studies were thoroughly performed using through Raman spectroscopy and electrical sheet resistance measurement. Our approach is thought to be worth considerable in order to enhance productivity of the CVD graphene in the industry.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.19 no.6
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• pp.298-304
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• 2009

The effect of the surface treatments on the high temperature properties of the Inconel 617, one of the promising candidate alloys for high temperature heat-transport system, has been studied. Various surface modification methods including a rapid thermal process(RTP), a hydrothermal treatment, and a physical vapor deposition($2{\mu}m$ thick TiAlN film by an arc discharge) were applied to the Inconel 617. The morphological and the structural properties of the surface-modified Inconel 617 samples after heat treatment at $1000^{\circ}C$ in the air were compared to find out whether inhomogeneous formation of $Cr_2O_3$ crust at the surface region was suppressed or not. TiAlN-coated Inconel 617 showed homogeneous microstructure and the lowest wear loss compared to bare, RTP- and hydrothermally-treated Inconel 617 by suppressing the $Cr_2O_3$ crust formation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.112-117
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• 2008

Vertical interconnection scheme using novel silicon-through-via for 3D MEMS devices or stacked package is proposed and fabricated to demonstrate its feasibility. The suggested silicon-through-via replaces electroplated copper, which is used as an interconnecting material in conventional through-via, with doped silicon. Adoption of doped silicon instead of metal eliminates thermal-mismatch-induced stress, which can make troubles in high temperature MEMS processes, such as wafer bonding and LP-CVD(low pressure chemical vapor deposition). Two silicon layers of $30{\mu}m$ thickness are stacked on the substrate. The through-via arrays with spacing $40{\mu}m$ and $50{\mu}m$ are fabricated successfully. Electrical characteristics of the through-via are measured and analyzed. The measured resistance of the silicon-through-via is $169.9\Omega$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.9
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• pp.916-923
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• 2004

In this paper, the strained Si$_{0.9}$Ge$_{0.1}$ epitaxial layers grown by a reduced pressure chemical vapor deposition (RPCVD) on Si (100) were characterized by Rutherford backscattering spectrometery (RBS) for the fabrication of an SiGe heterojunction bipolar transistor(HBT). RBS spectra of the ${Si}_0.9{Ge}_0.1$epitaxial layers grown on the Si substrates which were implanted with the phosphorus (P) ion and annealed at a temperature between $850^{\circ}C$ - $1000^{\circ}C$ for 30min were analyzed to investigate the post thermal annealing effect on the grown${Si}_0.9{Ge}_0.1$epitaxial layer quality. Although a damage of the substrates by P ion-implantation might be cause of the increase of RBS yield ratios, but any defects such as dislocation or stacking fault in the grown ${Si}_0.9{Ge}_0.1$ epitaxial layer were not found in transmission electron microscope (TEM) photographs. The post high temperature rapid thermal annealing (RTA) effects on the crystalline quality of the ${Si}_0.9{Ge}_0.1$ epitaxial layers were also analyzed by RBS. The changes in the RBS yield ratios were negligible for RTA a temperature between $900^{\circ}C$ - $1000^{\circ}C$for 20 sec, or $950^{\circ}C$for 20 sec - 60 sec. A SiGe HBT array shows a good Gummel characteristics with post RTA at $950^{\circ}C$ for 20 sec.sec.sec.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2009.05a
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• pp.167-169
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• 2009

We have carried out quantitative structure and property analysis of the nanoporous structures of low dielectric constant (low-k) carbon-doped silicon oxide (SiCOH) films, which were deposited with plasma enhanced chemical vapor deposition (PECVD) using vinyltrimethylsilane (VTMS), divinyldimethylsilane (DVDMS), and tetravinylsilane (TVS) as precursor and oxygen as an oxidant gas. We found that the SiCOH film using VTMS only showed well defined spherical nanopores within the film after thermal annealing at $450^{\circ}C$ for 4 h. The average pore radius of the generated nanopores within VTMS SiCOH film was 1.21 nm with narrow size distribution of 0.2. It was noted that thermally labile $C_{x}H_{y}$ phase and Si-$CH_3$ was removed to make nanopore within the film by thermal annealing. Consequently, this induced that decrease of average electron density from 387 to $321\;nm^{-3}$ with increasing annealing temperature up to $450^{\circ}C$ and taking a longer annealing time up to 4 h. However, the other SiCOH films showed featureless scattering profiles irrespective of annealing conditions and the decreases of electron density were smaller than VTMS SiCOH film. Because, with more vinyl groups are introduced in original precursor molecule, films contain more organic phase with less volatile characteristic due to the crosslinking of vinyl groups. Collectively, the presenting findings show that the organosilane containing vinyl group was quite effective to deposit SiCOH/$C_{x}H_{y}$ dual phase films, and post annealing has an important role on generation of pores with the SiCOH film.

• Current Photovoltaic Research
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• v.3 no.3
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• pp.80-84
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• 2015

We suggest new emitter formation method using solid-phase epitaxy (SPE); solid-phase epitaxy emitter (SEE). This method expect simplification and cost reduction of process compared with furnace process (POCl3 or BBr3). The solid-phase epitaxy emitter (SEE) deposited a-Si:H layer by radio-frequency plasma-enhanced chemical vapor deposition (RF-PECVD) on substrate (c-Si), then thin layer growth solid-phase epitaxy (SPE) using rapid thermal process (RTP). This is possible in various emitter profile formation through dopant gas ($PH_3$) control at deposited a-Si:H layer. We fabricated solar cell to apply solid-phase epitaxy emitter (SEE). Its performance have an effect on crystallinity of phase transition layer (a-Si to c-Si). We confirmed crystallinity of this with a-Si:H layer thickness and annealing temperature by using raman spectroscopy, spectroscopic ellipsometry and transmission electron microscope. The crystallinity is excellent as the thickness of a-Si layer is thin (~50 nm) and annealing temperature is high (<$900^{\circ}C$). We fabricated a 16.7% solid-phase epitaxy emitter (SEE) cell. We anticipate its performance improvement applying thin tunnel oxide (<2nm).

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.28.1-28.1
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• 2009

The superior properties of ZnO such as high exciton binding energy, high thermal and chemical stability, low growth temperature and possibility of wet etching process in ZnO have great interest for applications ranging from optoelectronics to chemical sensor. Particularly, vertically well-aligned ZnO nanorods on large areas with good optical and structural properties are of special interest for the fabrication of electronic and optical nanodevices. Currently, low-dimensional ZnO is synthesized by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), thermal evaporation, and sol.gel growth. Recently, our group has been reported about achievement the growth of Ga-doped ZnO nanorods using ZnO seed layer on p-type Si substrate by RF magnetron sputtering system at high rf power and high growth temperature. However, the crystallinity of nanorods deteriorates due to lattice mismatch between nanorods and Si substrate. Also, in the growth of oxide using sputtering, the oxygen flow ratio relative to argon gas flow is an important growth parameter and significantly affects the structural properties. In this study, Phosphorus (P) doped ZnO nanorods were grown on c-sapphire substrates without seed layer by radio frequency magnetron sputtering with various argon/oxygen gas ratios. The layer change films into nanorods with decreasing oxygen partial pressure. The diameter and length of vertically well-aligned on the c-sapphire substrate are in the range of 51-103 nm and about 725 nm, respectively. The photoluminescence spectra of the nanorods are dominated by intense near band-edge emission with weak deep-level emission.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.398-398
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• 2007

Most recently, the Liquid Crystal (LC) aligning capabilities achieved by ion beam exposure on the diamond-like carbon (DLC) thin film layer have been successfully studied. The DLC thin films have a high mechanical hardness, a high electrical resistance, optical transparency and chemical inertness. Nitrogen doped Diamond Like Carbon (NDLC) thin films exhibit properties similar to those of the DLC films and better thermal stability than the DLC films because C:N bonding in the NDLC film is stronger against thermal stress than C:H bonding in the DLC thin films. Moreover, our research group has already studied ion beam alignment method using the NDLC thin films. The nematic liquid crystal (NLC) alignment effects treated on the SiNx thin film layers using ion beam irradiation for three kinds of N rations was successfully studied for the first time. The SiNx thin film was deposited by plasma-enhanced chemical vapor deposition (PECVD) and used three kinds of N rations. In order to characterize the films, the atomic force microscopy (AFM) image was observed. The good LC aligning capabilities treated on the SiNx thin film with ion beam exposure for all N rations can be achieved. The low pretilt angles for a NLC treated on the SiNx thin film with ion beam irradiation were measure.

• Current Photovoltaic Research
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• v.10 no.2
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• pp.33-38
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• 2022

Planner configuration thin film solar cells (TFSCs) with SnS/CdS heterojunction performed a lower short-circuit current (J_SC). In this study, we have demonstrated a path to overcome deficiency in J_SC by the incorporation of Se in the SnS absorber. We carried out the incorporation of Se in VTD grown SnS absorber by rapid thermal annealing (RTA). The diffusion of Se is mostly governed by RTA temperature (T_RTA), also it is observed that film structure changes from cube-like to plate-like structure with T_RTA. The maximum J_SC of 23.1 mA cm^-2 was observed for 400℃ with an open-circuit voltage (V_OC) of 0.140 V for the same temperature. The highest performance of 2.21% with J_SC of 18.6 mA cm^-2, V_OC of 0.290 V, and fill factor (FF) of 40.9% is observed for a T_RTA of 300℃. In the end, we compare the device performance of Se- incorporated SnS absorber with pristine SnS absorber material, increment in J_SC is approximately 80% while a loss in V_OC of about 20% has been observed.