• Journal of the Microelectronics and Packaging Society
• /
• v.20 no.3
• /
• pp.75-80
• /
• 2013

According to advance of electronic packaging technology, electronic package becomes smaller. Miniaturization of package causes the temperature rise of package. This can degrade life of electronic device and generate the failure of electronic system. In this study, we proposed a new semi-embedded structure with micro pattern for maximizing heat dissipation. A proposed structure showed the characteristics which have maximum temperature lower than $20^{\circ}C$ compared with conventional structure. And also, in view of thermal stress and strain, our structure showed a remarkably low value compared with other ones. We expect that the new structure proposed in this work can be applied to an flip-chip package of the future.

• Journal of Power Electronics
• /
• v.9 no.4
• /
• pp.544-552
• /
• 2009

This paper presents a novel spring pressure contact interconnect technique for medium power integrated power electronics modules (IPEMs). The key technology of this interconnection is a spring which is made from Be-Cu alloy. By means of the string pressure contact, sufficient press-contact force and good electrical interconnection can be achieved. Another important advantage is that the spring exhibits excellent performance in enduring thermo-mechanical stress. In terms of manufacture procedure, it is also comparatively simple. A 4 kW half-bridge power inverter module is fabricated to demonstrate the performance of the proposed pressure contact technique. Electrical, thermal and mechanical test results of the packaged device are reported. The results of both the simulation and experiment have proven that a good performance can be achieved by the proposed pressure contact technique for the medium power IPEMs.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2000.04a
• /
• pp.43-55
• /
• 2000

In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology. Flip chip technology eliminates the need for wire bonding by redistributing the bond pads over the entire surface of the die. Instead of wires, the die is attached to the substrate utilizing a direct solder connection. Although several steps and processes are eliminated when utilizing flip chip technology, there are several new problems that must be overcome. The main issue is the mismatch in the coefficient of thermal expansion (CTE) of the silicon die and the substrate. This mismatch will cause premature solder Joint failure. This issue can be compensated for by the use of an underfill material between the die and the substrate. Underfill helps to extend the working life of the device by providing environmental protection and structural integrity. Flux residues may interfere with the flow of underfill encapsulants causing gross solder voids and premature failure of the solder connection. Furthermore, flux residues may chemically react with the underfill polymer causing a change in its mechanical and thermal properties. As flip chip packages decrease in size, cleaning becomes more challenging. While package size continues to decrease, the total number of 1/0 continue to increase. As the I/O increases, the array density of the package increases and as the array density increases, the pitch decreases. If the pitch is decreasing, the standoff is also decreasing. This paper will present the keys to successful flip chip cleaning processes. Process parameters such as time, temperature, solvency, and impingement energy required for successful cleaning will be addressed. Flip chip packages will be cleaned and subjected to JEDEC level 3 testing, followed by accelerated stress testing. The devices will then be analyzed using acoustic microscopy and the results and conclusions reported.

• Journal of the Microelectronics and Packaging Society
• /
• v.11 no.4 s.33
• /
• pp.13-22
• /
• 2004

In MEMS devices, packaging induced stress or stress induced structure deformation become increasing concerns since it directly affects the performance of the device. In this paper, deformation behavior of MEMS gyroscope package subjected to temperature change is investigated using high-sensitivity moire interferometry. Using the real-time moire setup, fringe patterns are recorded and analyzed at several temperatures. Temperature dependent analyses of warpages and extensions/contractions of the package are presented. Linear elastic behavior is documented in the temperature region of room temperature to $125^{\circ}C$. Analysis of the package reveals that global bending occurs due to the mismatch of thermal expansion coefficient between the chip, the molding compound and the PCB. Detailed global and local deformations of the package by temperature change are investigated, concerning the variation of natural frequency of MEMS gyro chip.

• Journal of Sensor Science and Technology
• /
• v.24 no.6
• /
• pp.379-384
• /
• 2015

An infrared image sensor is a core device in a thermal imaging system. The fabrication method of a focal plane array (FPA) is a key technology for a high resolution infrared image sensor. Each pixels in the FPA have $Si_3N_4/SiO_2$ membranes including legs to deposit bolometric materials and electrodes on Si readout circuits (ROIC). Instead of polyimide used to form a sacrificial layer, the feasibility of an amorphous silicon (${\alpha}-Si$) was verified experimentally in a $8{\times}8$ micro-bolometer array with a $50{\mu}m$ pitch. The elimination of the polyimide sacrificial layer hardened by a following plasma assisted deposition process is sometimes far from perfect, and thus requires longer plasma ashing times leading to the deformation of the membrane and leg. Since the amorphous Si could be removed in $XeF_2$ gas at room temperature, however, the fabricated micro-bolomertic structure was not damaged seriously. A radio frequency (RF) sputtered nickel oxide film was grown on a $Si_3N_4/SiO_2$ membrane fabricated using a low stress silicon nitride (LSSiN) technology with a LPCVD system. The deformation of the membrane was effectively reduced by a combining the ${\alpha}-Si$ and LSSiN process for a nickel oxide micro-bolometer.

• Journal of the Microelectronics and Packaging Society
• /
• v.16 no.2
• /
• pp.33-42
• /
• 2009

A polymer-based flexible neural probe was fabricated for monitoring of neural activities from a brain. To improve the insertion stiffness, a 5 ${\mu}m$ thick biocompatible Au layer was electroplated between the top and bottom polymer layers. The developed neural probe penetrated a gel whose elastic modulus is similar to that of a live brain tissue without any fracture, To minimize mechanical residual stress and bending from the probe, two new methods were employed: (1) use of a thermal annealing process after completing the device and (2) incorporation of multiple different layers to compensate the residual stress between top and bottom layers. Mechanical bending around the probe tip was clearly removed after employing the two processes. In electrical test, the developed probe showed a proper impedance value to record neural signals from a brain and the result remained the same for 72 hours. In simple in-vitro probe characterization, the probe showed a great removal of residual stress and an excellent recording performance. The in-vitro recording results did not change even after 1 week, suggesting that this electrode has the potential for great recording from neuron firing and long-term implant performance.

• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 2018.06a
• /
• pp.140-140
• /
• 2018

The 3D interconnect technologies have been appeared, as the density of Integrated Circuit (IC) devices increases. Through Silicon Via (TSV) process is an important technology in the 3D interconnect technologies. And the process is used to form a vertically electrical connection through silicon dies. This TSV process has some advantages that short length of interconnection, high interconnection density, low electrical resistance, and low power consumption. Because of these advantages, TSVs could improve the device performance higher. The fabrication process of TSV has several steps such as TSV etching, insulator deposition, seed layer deposition, metallization, planarization, and assembly. Among them, TSV metallization (i.e. TSV filling) was core process in the fabrication process of TSV because TSV metallization determines the performance and reliability of the TSV interconnect. TSVs were commonly filled with metals by using the simple electrochemical deposition method. However, since the aspect ratio of TSVs was become a higher, it was easy to occur voids and copper filling of TSVs became more difficult. Using some additives like an accelerator, suppressor and leveler for the void-free filling of TSVs, deposition rate of bottom could be fast whereas deposition of side walls could be inhibited. The suppressor was adsorbed surface of via easily because of its higher molecular weight than the accelerator. However, for high aspect ratio TSV fillers, the growth of the top of via can be accelerated because the suppressor is replaced by an accelerator. The substitution of the accelerator and the suppressor caused the side wall growth and defect generation. The suppressor was used as Single additive electrodeposition of TSV to overcome the constraints. At the electrochemical deposition of high aspect ratio of TSVs, the suppressor as single additive could effectively suppress the growth of the top surface and the void-free bottom-up filling became possible. Generally, copper was used to fill TSVs since its low resistivity could reduce the RC delay of the interconnection. However, because of the large Coefficients of Thermal Expansion (CTE) mismatch between silicon and copper, stress was induced to the silicon around the TSVs at the annealing process. The Keep Out Zone (KOZ), the stressed area in the silicon, could affect carrier mobility and could cause degradation of the device performance. Cobalt can be used as an alternative material because the CTE of cobalt was lower than that of copper. Therefore, using cobalt could reduce KOZ and improve device performance. In this study, high-aspect ratio TSVs were filled with cobalt using the electrochemical deposition. And the filling performance was enhanced by using the suppressor as single additive. Electrochemical analysis explains the effect of suppressor in the cobalt filling bath and the effect of filling behavior at condition such as current type was investigated.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.15 no.4
• /
• pp.1838-1843
• /
• 2014

Nanoimprint lithography (NIL) fabrication process is regarded as the main alternative to existing expensive photo-lithography in areas such as micro- and nano-electronics including optical components and sensors, as well as the solar cell and display device industries. Functional patterns, including anti-reflective moth-eye pattern, photonic crystal pattern, fabricated by NIL can improve the overall efficiency of such devices. To successfully imprint a nano-sized pattern, the process conditions such as temperature, pressure, and time should be appropriately selected. In this paper, a cavity-filling process of the moth-eye pattern during the thermal-NIL within the temperature range, where the polymer resist shows the viscoelastic behaviors with consideration of stress relaxation effect of the polymer, were investigated with three-dimensional finite element analysis. The effects of initial thickness of polymer resist and imprinting pressure on cavity-filling process has been discussed. From the analysis results it was found that the cavity filling can be completed within 100 s, under the pressure of more than 4 MPa.

• Journal of the Korean Magnetics Society
• /
• v.14 no.5
• /
• pp.163-168
• /
• 2004

We prepared ultra thin film structure of Si(100)/ $SiO_2$(200 nm)/Ta(5 nm)/Ni$_{80}$Fe$_{20/(l～15 nm)}$Ta(5 nm) using an inductively coupled plasma(ICP) helicon sputter. Magnetic properties and cross-sectional microstructures were investigated with a superconduction quantum interference device(SQUID) and a transmission electron microscope(TEM), respectively. We report that NiFe films of sub-3 nm thickness show the B$_{bulk}$ = 0 and B$_{surf}$=-3 ${\times}$ 10$^{-7}$(J/$m^2$). Moreover, Curie temperature may be lowered by decreasing thickness. Coercivity become larger as temperature decreased with 0.5 nm - thick Ta/NiFe interface intermixing. Our result implies that effective magnetic properties of magnetoelastic anisotropy, saturation magnetization, and coercivity may change abruptly in nano-thick films. Thus we should consider those abrupt changes in designing nano-devices such as MRAM applications.

• Journal of Korea Foundry Society
• /
• v.40 no.3
• /
• pp.85-96
• /
• 2020

The effect of an aluminum scrap addition ratio on the tensile and solidification cracking properties of the AC4A aluminum alloy in the as-cast state and heat-treated state were investigated in this study. Generally, the expected problem of using scrap in aluminum casting is an increase of hydrogen and Fe element inside the aluminum melt. Another issue is an oxide film which has a weak interface with the molten aluminum and acts as potent nucleation sites for internal porosity and crack initiation. Solidification cracking is one of the critical defects that must be resolved to produce high quality castings. A conventional evaluation method for solidification cracking is a relative and qualitative analysis method which does not provide quantitative data on the thermal stress in the solidification process. Therefore, a newly designed solidification cracking test apparatus was used in this study, and the device can provide quantitative data. As a result, after conducting experiments with different scrap addition ratios (0%, 20%, 35%, 50%), the tensile strengths and elongations in the as-cast state were 214, 187.7, 182.1 and 170.4MPa and 4.6%, 3.4%, 3.1% and 2.3%, respectively. In the case of the T6 heat-treated state, the tensile strengths and elongations were 314.9, 294.6, 293.1 and 271.1MPa and 5.4%, 4.6%, 3.8% and 3.1%, respectively. The strength of the solidification cracking was 3.1, 2.4, 2.2and 1.6MPa as the scrap addition ratio increases.