• Journal of the Microelectronics and Packaging Society
• /
• v.14 no.1
• /
• pp.27-31
• /
• 2007

The cpapcitors with MIM(metal-insulator-metal) structures using PVP gate insulation films were prepared for the application of flexible organic thin film transistors (OTFT). The co-polymer organic insulation films were synthesized by using PVP(poly-4-vinylphenol) as a solute and PGMEA(propylene glycol monomethyl ether acetate) as a solvent. The cross-linked PVP insulation films were also prepared by addition of poly(melamine-co-formaldehyde) as thermal hardener. The leakage current of the cross- linked PVP films was found to be about 1.3 nA on Al/PES(polyethersulfone) substrate, whereas, on ITO/ glass substrate was about 27.5 nA indicating improvement of the leakage current at Al/PES substrates. Also, the capacitances of all prepared samples on ITO/glass and Al/PES substrates w ere ranged from 1.0 to $1.2nF/cm^2$, showing very similar result with the calculated capacitance values.

• Journal of Information Display
• /
• v.4 no.2
• /
• pp.1-6
• /
• 2003

In this paper, we demonstrate that the organic electrophosphorescent device is driven by the organic thin film transistor with spin-coated photoacryl gate insulator. It was found that electrical output characteristics in our organic thin film transistors using the staggered-inverted top-contact structure showed the non-saturated slope in the saturation region and the sub-threshold nonlinearity in the triode region, where we obtained the maximum power luminance that was about 90 $cd/m^2$. Field effect mobility, threshold voltage, and on-off current ratio in 0.45 ${\mu}m$ thick gate dielectric layer were 0.17 $cm^2/Vs$, -7 V, and $10^6$ , respectively. In order to form polyimide as a gate insulator, vapor deposition polymerization process was also introduced instead of spin-coating process, where polyimide film was co-deposited by high-vacuum thermal evaporation from 4,4'-oxydiphthalic anhydride (ODPA) and 4,4'-oxydianiline (ODA) and cured at 150${\sqsubset}$for 1hr. It was also found that field effect mobility, threshold voltage, on-off current ratio, and sub-threshold slope with 0.45 ${\mu}m$ thick gate dielectric films were 0.134 $cm^2/Vs$, -7 V, and $10^6$ A/A, and 1 V/decade, respectively.

• Journal of Ceramic Processing Research
• /
• v.20 no.5
• /
• pp.484-489
• /
• 2019

VO2 is an attractive candidate as a transition metal oxide switching material as a selection device for reduction of sneak-path current. We demonstrate deposition of nanoscale VO2 thin films via thermal atomic layer deposition (ALD) with H2O reactant. Using this method, we demonstrate VO2 thin films with high-quality characteristics, including crystallinity, reproducibility using X-ray diffraction, and X-ray photoelectron spectroscopy measurement. We also present a method that can increase uniformity and thin film quality by splitting the pulse cycle into two using scanning electron microscope measurement. We demonstrate an ON / OFF ratio of about 40, which is caused by metal insulator transition (MIT) of VO2 thin film. ALD-deposited VO2 films with high film uniformity can be applied to next-generation nonvolatile memory devices with high density due to their metal-insulator transition characteristic with high current density, fast switching speed, and high ON / OFF ratio.

• Proceedings of the KIEE Conference
• /
• 2009.07a
• /
• pp.1349_1350
• /
• 2009

Thin films of pp(ST-Co-VA) were fabricated by plasma deposition polymerization (PVDPM) technique. Properties of the plasma polymerized pp(ST-Co-VA) thin films were investigated for application to semiconductor device as insulator. Thickness, dielectric property, composition of the pp(ST-Co-VA) thin films were investigated considering the relationship with preparation condition such as gas pressure and deposition time. In order to verify the possibility of application to organic thin film transistor, a pentacene thin film was deposited on the pp(ST-Co-VA) insulator by vacuum thermal evaporation technique. Crystalline property of the pentacene thin film was investigated by XRD and SEM, FT-IR. Surface properties at the pp(ST-Co-VA)/pentacene interface was investigated by contact angle measurement. The pp(ST-Co-VA) thin film showed a high-k (k=4.6) and good interface characteristic with pentacene semiconducting layer, which indicates that it would be a promising material for organic thin film transistor (OTFT) application.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.07b
• /
• pp.830-833
• /
• 2003

This paper describes the fabrication and characteristics of 3C-SiCOI sotctures by SDB and etch-back technology for high-temperature MEMS applications. In this work, insulator layers were formed on a heteroepitaxial 3C-SiC film grown on a Si(001) wafer by thermal wet oxidation and PECVD process, successively. The pre-bonding of two polished PECVD oxide layers made the surface activation in HF and bonded under applied pressure. The wafer bonding characteristics were evaluated by the effect of HF concentration used in the surface treatment on the roughness of the oxide and pre-bonding strength. Hydrophilic character of the oxidized 3C-SiC film surface was investigated by ATR-FTIR. The strength of the bond was measured by tensile strengthmeter. The bonded interface was also analyzed by SEM. The properties of fabricated 3C-SiCOI structures using etch-back technology in TMAH solution were analyzed by XRD and SEM. These results indicate that the 3C-SiCOI structure will offers significant advantages in the high-temperature MEMS applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.04b
• /
• pp.179-182
• /
• 2004

ZnO varistor for transmission class arrester$({\Phi}65{\times}20mm)$ of 10kA(Class 3) grade was recently developed in korea and is tested for the properties by switching surge operating duty test to know the line discharge class and complex surge property in electric properties. To find out changing rate of residual voltage before and after lightning impulse residual voltage testing, the sample is cool to room temperature after finishing switching surge operating duty test, and the rate is good as 1.0~1.7%. The element had been considered as applicable ZnO varistor for electricity transmission from the test results of state conterl, switching surge operating duty, thermal stability and above test. But various test should be required for actual application because this is a part of the to be needed for application.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.08a
• /
• pp.202-202
• /
• 2010

최근 반도체 소자의 미세화에 따라, 단채널 효과에 의한 누설전류 및 소비전력증가 등이 문제가 되고 있다. DRAM의 경우, 캐패시터 영역의 축소문제가 소자집적화를 방해하는 요소로 작용하고 있다. 1T-DRAM은 기존의 DRAM과 달리 캐패시터 영역을 없애고 상부실리콘의 중성영역에 전하를 저장함으로써 소자집적화에 구조적인 이점을 갖는다. 또한 silicon-on-insulator (SOI) 기판을 이용할 경우, 뛰어난 전기적 절연 특성과 기생 정전용량의 감소, 소자의 저전력화를 실현할 수 있다. 본 연구에서는 silicon-germanium-on-insulator (SGOI) 기판을 이용한 1T-DRAM의 열처리온도에 따른 특성 변화를 평가하였다. 기존의 SOI 기판을 이용한 1T-DRAM과 달리, SGOI 기판을 사용할 경우, strained-Si 층과 relaxed-SiGe 층간의 격자상수 차에 의한 캐리어 이동도의 증가효과를 기대할 수 있다. 하지만 열처리 시, SiGe층의 Ge 확산으로 인해 상부실리콘 및 SiGe 층의 두께를 변화시켜, 소자의 특성에 영향을 줄 수 있다. 열처리는 급속 열처리 공정을 통해 $850^{\circ}C$와 $1000^{\circ}C$로 나누어 30초 동안 N2/O2 분위기에서 진행하였다. 그리고 Programming/Erasing (P/E)에 따라 달라지는 전류의 차를 감지하여 제작된 1T-DRAM의 메모리 특성을 평가하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.16 no.8
• /
• pp.700-704
• /
• 2003

This paper describes on characteristics of 2" 3C-SiC wafer bonding using PECVD (plasma enhanced chemical vapor deposition) oxide and HF (hydrofluoride acid) for SiCOI (SiC-on-Insulator) structures and MEMS (micro-electro-mechanical system) applications. In this work, insulator layers were formed on a heteroepitaxial 3C-SiC film grown on a Si (001) wafer by thermal wet oxidation and PECVD process, successively. The pre-bonding of two polished PECVD oxide layers made the surface activation in HF and bonded under applied pressure. The bonding characteristics were evaluated by the effect of HF concentration used in the surface treatment on the roughness of the oxide and pre-bonding strength. Hydrophilic character of the oxidized 3C-SiC film surface was investigated by ATR-FTIR (attenuated total reflection Fourier transformed infrared spectroscopy). The root-mean-square suface roughness of the oxidized SiC layers was measured by AFM (atomic force microscope). The strength of the bond was measured by tensile strength meter. The bonded interface was also analyzed by IR camera and SEM (scanning electron microscope), and there are no bubbles or cavities in the bonding interface. The bonding strength initially increases with increasing HF concentration and reaches the maximum value at 2.0 ％ and then decreases. These results indicate that the 3C-SiC wafer direct bonding technique will offers significant advantages in the harsh MEMS applications.ions.

• Korean Journal of Materials Research
• /
• v.16 no.10
• /
• pp.652-655
• /
• 2006

A direct wafer bonding process necessary for GaAs-on-insulator (GOI) fabrication with high thermal annealing temperatures was studied by using PECVD oxides between gallium arsenide and silicon wafers. In order to apply some uniform pressure on initially-bonded wafer pairs, a graphite sample holder was used for wafer bonding. Also, a tool for measuring the tensile forces was fabricated to measure the wafer bonding strengths of both initially-bonded and thermally-annealed samples. GaAs/$SiO_2$/Si wafers with 0.5-$\mu$m-thick PECVD oxides were annealed from $100^{\circ}C\;to\;600^{\circ}C$. Maximum bonding strengths of about 84 N were obtained in the annealing temperature range of $400{\sim}500^{\circ}C$. The bonded wafers were not separated up to $600^{\circ}C$. As a result, the GOI wafers with high annealing temperatures were demonstrated for the first time.

• Safety and Health at Work
• /
• v.11 no.4
• /
• pp.405-417
• /
• 2020

Background: Electrical socket outlets are used continuously until a failure occurs because they have no indication of manufacturing date or exchange specifications. For this reason, 659 electrical fires related to electrical socket outlets broke out in the Republic of Korea at 2018 only, an increase year on year. To reduce electrical fires from electrical socket outlets, it is necessary to perform an accelerated test and analyze the thermal, insulation resistance, and material properties of electrical socket outlets by installation years. Methods: Thermal characteristics were investigated by measured the temperature increase of electrical socket outlets classified according to year with variation of the current level. Insulation resistance characteristics was measured according to temperature for an electrical socket outlets by their years of use. Finally, to investigate the thermal and insulation resistance characteristics in relation to outlet aging, this study analyzed electrical socket outlets' conductor surface and content, insulator weight, and thermal deformation temperature. Results: Analysis showed, regarding the thermal characteristics, that electrical socket outlet temperature rose when the current value increased. Moreover, the longer the time that had elapsed since an accelerated test and installation, the higher the electrical socket outlet temperature was. With respect to the insulation resistance properties, the accelerated test (30 years) showed that insulation resistance decreased from 110 ℃. In relation to the installation year (30 years), insulation resistance decreased from 70 ℃, which is as much as 40 ℃ lower than the result found by the accelerated test. Regarding the material properties, the longer the elapsed time since installation, the rougher the surface of conductor contact point was, and cracks increased. Conclusion: The 30-year-old electrical socket outlet exceeded the allowable temperature which is 65 ℃ of the electrical contacts at 10 A, and the insulation resistance began to decrease at 70 ℃. It is necessary to manage electrical socket outlets that have been installed for a long time.