• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.16 no.6
• /
• pp.454-464
• /
• 2023

This paper proposes a low-power 8-bit asynchronous SAR ADC with a sampling rate of 1 MS/s for sensor node applications. The ADC uses bootstrapped switches to improve linearity and applies a VCM-based CDAC switching technique to reduce the power consumption and area of the DAC. Conventional synchronous SAR ADCs that operate in synchronization with an external clock suffer from high power consumption due to the use of a clock faster than the sampling rate, which can be overcome by using an asynchronous SAR ADC structure that handles internal comparisons in an asynchronous manner. In addition, the SAR logic is designed using dynamic logic circuits to reduce the large digital power consumption that occurs in low resolution ADC designs. The proposed ADC was simulated in a 180-nm CMOS process, and at a 1.8 V supply voltage and a sampling rate of 1 MS/s, it consumed 46.06 𝜇W of power, achieved an SNDR of 49.76 dB and an ENOB of 7.9738 bits, and obtained a FoM of 183.2 fJ/conv-step. The simulated DNL and INL are +0.186/-0.157 LSB and +0.111/-0.169 LSB.

• Journal of IKEEE
• /
• v.12 no.3
• /
• pp.176-183
• /
• 2008

The high efficiency power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device is proposed in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. DTMOS with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuits consist of a saw-tooth generator, a band-gap reference circuit, an error amplifier and a comparator circuit as a block. The Saw-tooth generator is made to have 1.2 MHz oscillation frequency and full range of output swing from ground to supply voltage(VDD:3.3V). The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on Voltage-mode PWM control circuits and low on-resistance switching device, achieved the high efficiency near 95% at 100mA output current. And DC-DC converter is designed with LDO in stand-by mode which fewer than 1mA for high efficiency.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.40 no.1
• /
• pp.19-29
• /
• 2003

This paper proposes a CMOS readout circuit for uncooled micro-bolometer arrays adopting a four-point step calibration technique. The proposed readout circuit employing an 11b analog-to-digital converter (ADC), a 7b digital-to-analog converter (DAC), and an automatic gain control circuit (AGC) extracts minute infrared (IR) signals from the large output signals of uncooled micro-bolometer arrays including DC bias currents, inter-pixel process variations, and self-heating effects. Die area and Power consumption of the ADC are minimized with merged-capacitor switching (MCS) technique adopted. The current mirror with high linearity is proposed at the output stage of the DAC to calibrate inter-pixel process variations and self-heating effects. The prototype is fabricated on a double-poly double-metal 1.2 um CMOS process and the measured power consumption is 110 ㎽ from a 4.5 V supply. The measured differential nonlinearity (DNL) and integrat nonlinearity (INL) of the 11b ADC show $\pm$0.9 LSB and $\pm$1.8 LSB, while the DNL and INL of the 7b DAC show $\pm$0.1 LSB and $\pm$0.1 LSB.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.12
• /
• pp.2366-2373
• /
• 2007

In this paper, a low-power and small-area asynchronous 1 kilobit EEPROM for passive UHF RFID tag chips is designed with $0.18{\mu}m$ EEPROM cells. As small area solutions, command and address buffers are removed since we design asynchronous I/O interface and data output buffer is also removed by using separate I/O. To supply stably high voltages VPP and VPPL used in the cell array from low voltage VDD, Dickson charge pump is designed with schottky diodes instead of a PN junction diodes. On that account, we can decrease the number of stages of the charge pump, which can decrease layout area of charge pump. As a low-power solution, we can reduce write current by using the proposed VPPL power switching circuit which selects each needed voltage at either program or write mode. A test chip of asynchronous 1 kilobit EEPROM is fabricated, and its layout area is $554.8{\times}306.9{\mu}m2$., 11% smaller than its synchronous counterpart.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.16 no.4
• /
• pp.633-642
• /
• 2021

Growing demand for electricity, when combined with the need to limit carbon emissions, drives a huge increase in renewable energy industry. In the electric power system, electricity supply always needs to be balanced with electricity demand and network losses to maintain safe, dependable, and stable system operation. There are three broad challenges when it comes to a power system with a high penetration of renewable energy: transient stability, small signal stability, and frequency stability. Transient stability analyze the system response to disturbances such as the loss of generation, line-switching operations, faults, and sudden load changes in the first several seconds following the disturbance. Small signal stability refers to the system's ability to maintain synchronization between generators and steady voltages when it is subjected to small perturbations such as incremental changes in system load. Frequency stability refers to the ability of a power system to maintain steady frequency following a severe system upset resulting in significant imbalance between generation and load. In this paper, we discusses these stability using system simulation by renewable energy deployment plan, and also analyses the influence of the renewable energy sources to the grid stability.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.15 no.4
• /
• pp.913-920
• /
• 2011

In this paper, a logic process based 1-kbit EEPROM IP for RFID tag chips of 900MHz is designed. The cell array of the designed 1-kbit EEPROM IP is arranged in a form of four blocks of 16 rows x 16 columns, that is in a two-dimensional arrangement of one-word EEPROM phantom cells. We can reduce the IP size by making four memory blocks share CG (control gate) and TG (tunnel gate) driver circuits. We propose a TG switch circuit to supply respective TG bias voltages according to operational modes and to keep voltages between devices within 5.5V in terms of reliability in order to share the TG driver circuit. Also, we can reduce the power consumption in the read mode by using a partial activation method to activate just one of four memory blocks. Furthermore, we can reduce the access time by making BL (bit line) switching times faster in the read mode from reduced number of cells connected to each column. We design and compare two 1-kbit EEPROM IPs, two blocks of 32 rows ${\times}$ 16 columns and four blocks of 16 rows ${\times}$ 16 columns, which use Tower's $0.18{\mu}m$ CMOS process. The four-block IP is smaller by 11.9% in the layout size and by 51% in the power consumption in the read mode than the two-block counterpart.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.13 no.9
• /
• pp.4177-4185
• /
• 2012

LEDs are becoming the most suitable candidate replacing traditional fluorescent lamps because of its eco-friendly characteristics. LEDs are also actively used to design green building system and to make outdoor billboard as a back-light system due to its high energy efficiency. In this paper, we have developed AC direct driver for $12{\times}12$ FLB(flexible LED board) and LED flat light without SMPS. It has LID-PC-R101B driver IC that can support the high power factor and be composed of LED switching circuit in group. Also, an elaborate system designs can guarantee a high luminous efficiency, a high reliability and a low power consumption. The proposed FLB has the ultra slim shape of $450{\times}450$ mm, width of 4 mm and weight of 280 g. In the end, we have developed a prototype of FLB for billboard and flat light for room lighting with AC direct driver iposrder to verify the performance of the proposed system.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.15 no.2
• /
• pp.103-110
• /
• 2010

In this paper, a new mode changeable asymmetric full bridge dc/dc converter is proposed to solve the freewheeling current problem of the conventional zero voltage switching(ZVS) phase shift full bridge(PSFB) dc/dc converter of low output voltage and high output current applications. The proposed converter is operated as an asymmetric full bridge converter when the duty cycle is less than 50% and active clamp full bridge converter when the duty cycle is greater than 50%. As a result, since its freewheeling current is eliminated, the conduction loss is lower than that of the conventional ZVS PSFB dc/dc converter. Moreover, ZVS of all power switches can be ensured along a wide load ranges and output current ripple is very small. Therefore, high efficiency of the proposed converter can be achieved. Especially since its operation mode is changed to the active clamp full bridge converter during hold up time and can be operated with 50~100% duty ratio, it can produce the stable output voltage along wide input voltage range. The operational principles, theoretical analysis and design considerations are presented. To confirm the operation, validity and features of the proposed converter, experimental results from a 1.2kW($400V_{dc}/12V_{dc}$) prototype are presented.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.11
• /
• pp.13-20
• /
• 2008

In this paper, an 1.8V 12-bit 10MSPS CMOS A/D converter (ADC) is described. The architecture of the proposed ADC is based on a folding and interpolation using an even folding technique. For the purpose of improving SNR, cascaded-folding cascaded-interpolation technique, distributed track and hold are adapted. Further, a digital encoder algorithm is proposed for efficient digital process. The chip has been fabricated with $0.18{\mu}m$ 1-poly 4-metal n-well CMOS technology. The effective chip area is $2000{\mu}m{\times}1100{\mu}m$ and it consumes about 250mW at 1.8V power supply. The measured SNDR is about 46dB at 10MHz sampling frequency.

• IEIE Transactions on Smart Processing and Computing
• /
• v.4 no.5
• /
• pp.371-378
• /
• 2015

In this paper, a different type of pulse width modulation (PWM) control scheme for a buck converter is introduced. The proposed buck converter uses PWM with frequency hopping and a low quiescent.current low dropout (LDO) voltage regulator with a power supply rejection ratio enhancer to reduce high spurs, harmonics and output voltage ripples. The low quiescent.current LDO voltage regulator is not described in this paper. A three-bit binary-to-thermometer decoder scheme and voltage ripple controller (VRC) is implemented to achieve low voltage ripple less than 3mV to increase the efficiency of the buck converter. An internal clock that is synchronized to the internal switching frequency is used to set the hopping rate. A center frequency of 2.5MHz was chosen because of the bluetooth low energy (BLE) application. This proposed DC-DC buck converter is available for low-current noise-sensitive loads such as BLE and radio frequency loads in portable communications devices. Thus, a high-efficiency and low-voltage ripple is required. This results in a less than 2% drop in the regulator's efficiency, and a less than 3mV voltage ripple, with -26 dBm peak spur reduction operating in the buck converter.