• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.378-384
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• 2013

In this paper, a CMOS temperature sensor is proposed to measure the internal temperature of a chip. The temperature sensor consists of a proportional-to-absolute-temperature (PTAT) circuit for a temperature sensing part and a 4-bit analog-to-digital converter (ADC) for a digital interface. The PTAT circuit with the compact area is designed by using a vertical PNP architecture in the CMOS process. To reduce sensitivity of temperature variation in the digital interface circuit of the proposed temperature sensor, a 4-bit successive approximation (SA) ADC using the minimum analog circuits is used. It uses a capacitor-based digital-to-analog converter and a time-domain comparator to minimize power consumption. The proposed temperature sensor was fabricated by using a $0.25{\mu}m$ 1-poly 6-metal CMOS process with a 2.5V supply, and its operating temperature range is from 50 to $150^{\circ}C$. The area and power consumption of the fabricated temperature sensor are $130{\times}390{\mu}m^2$ and $868{\mu}W$, respectively.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.37-42
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• 2000

In this paper, The high-speed, low-Power analog-to-digital conversion structure is proposed using the pipelined comparator away for high-speed conversion rate and the successive- approximation structure for low-power consumption. This structure is the successive-approximation structure using pipelined comparator array to change the reference voltage during the holding time. An 8-bit 10MS/s analog-to-digital converter is designed using 0.8${\mu}{\textrm}{m}$ CMOS technology. The INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 41㏈ at a sampling rate of 10MHz with 100KHz sine input signal. The Power consumption is 4.14㎽ at 10MS/s.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1259-1264
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• 1999

In this paper, the High-speed, Low-power Analog-Digital Conversion Archecture is porposed using the Pipelined archecture for High-speed conversion rate and the Successive-Approximation archecture for Low-power consumption. This archecture is the Successive-Approximation archecture using Pipelined Comparator array to change reference voltage during Holding Time. The Analog-to-Digital Converter for video processing is designed using 0.8${\mu}{\textrm}{m}$ CMOS tchnology. When an 6-bit 10MS/s Analog-to-Digital Converter is simulatined, the INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 37dB at a sampling rate of 10MHz with 100KHz sine input signal. The power consumption is 1.46mW at 10MS/s. When an 8-bit 10MS/s Analog-to Digital Converter is simulatined, the INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 41dB at a sampling rate of 100MHz with 100KHz sine input signal. The power consumption is 4.14m W at 10MS/s.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.5
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• pp.1-9
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• 1981

Experimental results on a 4-bit charge-coupled A/D converter are described. Major operations in the successive approximation algorithm are implemented in a monolithic chip, CCADC, which was fabricated usir p-channel CCD technology, with its die size of 4,200 mil2 Typical operating frequency range has been found out to be from 500Hz to 200kHz. In that frequency range, no missing code has been found in the whole signal range of 2.4 volts for ramp signal slewing at 1 LSB/(sampling time). A discussion is made on several layout techniques to conserve the nominal binary ratio of (8:4:2:1) among the areas of four adjacent potential wells (M wells), whose charge storing capacities correspond to each bit magnitude - 3.6 pC, 1.8 pC, 0.9 pC, and 0.45 pC nominal in the order of MSB to the LSB. The effect of 'dump slot', which is responsible for the excessive nonlinearity (2$\frac{1}{2}$LSB) in the A/D converter, is explained. A novel input scheme called 'slot zero insertion' to circumvent the deleterious effects of the dump slot is described with the experimental results.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.59-66
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• 2015

In this paper, we propose a method of improving the light-load efficiency of DC-DC buck converter using 4bit SAR-ADC (Successive Approximation ADC) for a LDO or a power transistor size selection technique. The proposed circuit selects power transistor sizes depending on load current so that improves the light-load efficiency of the DC-DC buck converter. For this, we select the power transistor size with a cross point of the switching loss and the conduction loss. Also, when the IC operates in standby mode or sleep mode, a LDO mode is selected for improving the efficiency. The proposed circuit selects power transistor sizes(X1, X2, X4, X8) with 4 bits and its efficiency is higher about the maximum of 25% at the light-load than that of a single transistor size. Input voltage and output voltage are 5V and 3.3V for maximum load currents of 500mA.

• Journal of IKEEE
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• v.24 no.3
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• pp.719-726
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• 2020

A threshold-voltage sensing circuit is proposed to compensate for pixel aging in active matrix organic light-emitting diodes. The proposed threshold-voltage sensing circuit consists of sample-hold (S/H) circuits and a single-ended successive approximation register (SAR) analog-to-digital converter (ADC) with a resolution of 10 bits. To remove a scale down converter of each S/H circuit and a voltage gain amplifier with a signl-to-differentail converter, the middle reference voltage calibration and input range calibration for the single-ended SAR ADC are performed in the capacitor digital-to-analog converter and reference driver. The proposed threshold-voltage sensing circuit is designed by using a 180-nm CMOS process with a supply voltage of 1.8 V. The ENOB and power consimption of the single-ended SAR ADC are 9.425 bit and 2.83 mW, respectively.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.10
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• pp.4923-4939
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• 2019

In this paper, a secure transmission scheme based on the artificial noise is proposed for D2D communications underlaying the full-duplex cellular network, and a secure power allocation scheme to maximize the overall secrecy rate of both the cellular user and D2D transmitter node is presented. Firstly, the full-duplex base station transmits the artificial noise to guarantee the secure communications when it receives signals of cellular uplinks. Under this secure framework, it is found that improving the transmission power of the cellular user or the D2D transmitter node will degrade the secrecy rate of the other, although will improve itself secrecy rate obviously. Hence, a secure power allocation scheme to maximize the overall secrecy rate is presented subject to the security requirement of the cellular user. However, the original power optimization problem is non-convex. To efficiently solve it, we recast the original problem into a convex program problem by utilizing the proper relaxation and the successive convex approximation algorithm. Simulation results evaluate the effectiveness of the proposed scheme.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.130-137
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• 2013

This paper presents analog front-end(AFE) circuits for bio-potential measurement. The proposed AFE is composed of IA(instrument amplifier), BPF(band-pass filter), VGA(variable gain amplifier) and SAR(successive approximation register) type ADC. The low gm(LGM) circuits with current division technique and Miller capacitance with high gain amplifier enable IA to implement on-chip AC-coupling without external passive components. Spilt capacitor array with capacitor division technique and asynchronous control make the 12-b ADC with low power consumption and small die area. The total current consumption of proposed AFE is 6.3uA at 1.8V.

• Phonetics and Speech Sciences
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• v.5 no.2
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• pp.25-31
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• 2013

This study examined cross-generational changes in the vowel system of Seoul Korean. Acoustic analyses of the vowel formants of /o/ and /u/, and their Euclidean distances in the vowel space were undertaken to explore an on-going merger of these two vowels as proposed in previous acoustic studies and a phonological analysis by Chae (1999). A robust cross-generational change of /o/ and /u/ was found, more evident for female speakers than for male speakers. For female speakers, with each successive generation, /o/ became increasingly approximated with /u/, regardless of the syllable positions that the target vowels were posited, whereas the cross-generational differences in the Euclidean distances were only shown in the second syllable position for the male speakers. These results demonstrate that 1) women are more advanced than men in the on-going approximation of /o/ and /u/; 2) the approximation of /o/ and /u/ is common in the non-initial position. Taken together, the merger of /o/ and /u/ appears to be in progress in Seoul Korean.

• Journal of the Korean Chemical Society
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• v.21 no.5
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• pp.362-371
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• 1977

In this paper application of the projection operator technique to the study of NMR absorption line shape and free induction decay curve is explored. It is found that the projection operator technique can provide a convenient means for deriving a set of hierarchy equations which may serve as a good starting point for theoretical calculation of the absorption line and free induction decay function by successive approximation or by an appropriate decoupling approximation. A brief review of linear response theory of NMR line shape and the relation between the absorption line shape and free induction decay function are also described.