• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.541-546
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• 2008

In this paper, conduction phenomena have been considered for nano structure double gate MOSFET, using the analytical model. The Possion equation is used to analytical model. The conduction mechanisms to have an influence on current conduction are thermionic emission and tunneling current, and subthreshold swings of this paper are compared with those of two dimensional simulation to verify this model. The deviation of current path and the influence of current path on subthreshold swing have been considered according to the dimensional parameters of double gate MOSFET, i.e. gate length, gate oxide thickness, channel thickness. The optimum channel doping concentration is determined as the deviation of conduction path is considered according doping concentration.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.445-447
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• 2016

Performance comparison between Tunneling Field-Effect Transistors (TFETs) was examined when three types of device parameter of double-gate TFET (DG-TFET) and single-gate TFET (SG-TFET) are varied. When the channel length is over 30 nm, silicon thickness is below 20 nm, and a gate insulator thickness decreases, the performance of $I_{on}$ and SS in SG-TFETs and DG-TFETs enhances. It shows that the performance of the DG-TFETs is improved than that of SG-TFETs at three types of device parameter.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.3
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• pp.177-182
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• 2013

Transparent thin film transistors (TTFT) were fabricated on $N^+$ Si wafers. $SiO_2$, $Si_3N_4/SiO_2$ and $Al_2O_3/SiO_2$ grown on the wafers were used as gate insulators. The rf magnetron sputtered zinc tin oxide (ZTO) films were adopted as active layers. $N^+$ Si wafers were wet-oxidized to grow $SiO_2$. $Si_3N_4$ and $Al_2O_3$ films were deposited on the $SiO_2$ by plasma enhanced chemical vapor deposition (PECVD) and atomic layer deposition (ALD), respectively. The mobility, $I_{on}/I_{off}$ and subthreshold swing (SS) were obtained from the transfer characteristics of TTFTs. The properties of gate insulators were analyzed by comparing the characteristics of TTFTs. The property variation of the ZTO TTFTs with time were observed.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.240.1-240.1
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• 2013

본 연구에서는 Symmetric NMOSFET의 channel length에 따른 전기적 특성 분석에 관한 연구를 진행하였다. 특성 분석에 사용된 소자의 Gate oxide 두께는 6 nm 이며, 채널 Width/Length는 각각 10/10 ${\mu}m$, 10/0.2 ${\mu}m$ 이다. Drain Avalanche Hot Carrier(DAHC) 테스트를 진행하기 위하여 각각 스트레스 조건을 추출하였고, 조건에 해당되는 스트레스를 1700초 동안 인가하였다. 스트레스 후, Channel length가 10 ${\mu}m$과 0.2 ${\mu}m$인 두 소자의 특성을 측정, 분석결과 10 ${\mu}m$의 소자의 경우 문턱전압(VT)과 Subthreshold swing (SS)의 변화가 없었지만 0.2 ${\mu}m$의 소자의 경우 0.42V의 (from 0.67V to 1.09V) 문턱전압 변화 (VTH)와 71 mV/dec (from 79 mV/dec to 150 mV/dec))의 Swing (SS)변화를 보여 스트레스 후에 Interface trap이 증가하였음을 알 수 있다. off-state leakage current를 측정 결과 0.2 ${\mu}m$ 의 경우 leakage current의 양이 증가하였음을 알 수 있고 이는 드레인 부근에 증가된 interface trap에 의한 현상으로 판단된다. 상기 결과와 같이 DAHC 스트레스에 의한 소자의 열화 현상은 Channel length가 짧을수록 더 크게 의존하는 것을 확인하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.61-61
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• 2009

P-type SGS-TFTs with 10 ${\mu}m$ channel length and two channel widths; $W_1=5{\mu}m$ and $W_2=10{\mu}m$ which has gate insulator made of 20nm $SiO_2$ and 80nm SiNx was fabricated and the electrical properties of them were measured. The field-effect mobility was increased from 95.84 to 104.19 $cm^2/V-s$ and threshold voltage also increased from -0.802 V to -0.954 V, when channel width is increased from5 ${\mu}m$ to 10 ${\mu}m$. Subthreshold swing decreased from 0.418 to 0.343 V/dec and $I_{on/off}$ ratio increased from $4.77{\times}10^7$ to $7.30{\times}10^7$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.62-62
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• 2009

Electrical properties of SGS-TFT with 5/5 ${\mu}m$ channel width and length which gate insulator is made of 20nm $SiO_2$ and 80nm $SiN_x$ was fabricated and measured at various temperatures. The field-effect mobility was decreased from 86.25 to 80.42 $cm^2/Vs$ and threshold voltage also decreased from -1.5792 to -1.0492 V, when temperature is increased from room temperature to $100^{\circ}C$. Subthreshold swing, also, increased from 0.3212 to 0.4818 V/dec and $I_{on/off}$ ratio decreased from $5.05{\times}10^7$ to $6.93{\times}10^5$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.36-36
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• 2009

In this work, we describe a method to fabricate the Pt-silicided SB-MOSFETs with a n-type Silicon-On-Insulator (SOI) substrate as an active layer and demonstrate their electrical and structural properties. The fabricated SB-MOSFETs have novel structure and metal gate without sidewall. The gate oxide with a thickness of 7 nm was deposited by sputtering. Also, this fabrication processes were carried out below $500^{\circ}C$. As a result, Subthreshold swing value and on/off ratio of Fabricated SB MOSFETs was 70 [mV/dec] and $10^8$.

• Korean Journal of Materials Research
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• v.28 no.8
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• pp.440-444
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• 2018

An effective cleaning method for Ni removal in Ni-induced lateral crystallization(Ni-MILC) poly-Si TFTs and their electrical properties are investigated. The HCN cleaning method is effective for removal of Ni on the crystallized Si surface, while the nitric acid treatment results decrease by almost two orders of magnitude in the Ni concentration due to effective removal of diffused Ni mainly in the poly-Si grain boundary regions. Using the HCN cleaning method after the nitric acid treatment, re-adsorbed Ni on the Si surfaces is effectively removed by the formation of Ni-cyanide complexions. After the cleaning process, important electrical properties are improved, e.g., the leakage current density from $9.43{\times}10^{-12}$ to $3.43{\times}10^{-12}$ A and the subthreshold swing values from 1.37 to 0.67 mV/dec.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.204.1-204.1
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• 2015

We studied the electrical properties and gate bias stress (GBS) stability of thin film transistors (TFTs) with multi-stacked InZnO layers. The InZnO TFTs were fabricated via solution process and the In:Zn molar ratio was 1:1. As the number of InZnO layers was increased, the mobility and the subthreshold swing (S.S) were improved, and the threshold voltage of TFT was reduced. The TFT with three-layered InZnO showed high mobility of $21.2cm^2/Vs$ and S.S of 0.54 V/decade compared the single-layered InZnO TFT with $4.6cm^2/Vs$ and 0.71 V/decade. The three-layered InZnO TFTs were relatively unstable under negative bias stress (NBS), but showed good stability under positive bias stress (PBS).

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.11a
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• pp.30.2-30.2
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• 2009

본 연구에서는 stamping법을이용하여 절연막에 실리콘 나노와이어를 embed시킨 field-effect transistor(FET) 소자의 전기적 특성에 대하여 분석하였다. Stamping법은 나노와이어를 이용한 소자를 제작하는데 있어 쉽고 경제적인 방법으로 최근 많이 사용되고 있는데, 이 방법을 이용하여 나노와이어를 절연막에 embed 시켰다. 이때, 사용한 실리콘 나노와이어는 무전해 식각법을 통하여 합성하였다. 식각 시간을 조절하여 나노와이어의 길이가 $100{\mu}m$ 정도가 되도록 하였고, 나노와이어의 지름은 정제를 통하여 20 ~ 200nm내로 조절하였다. FET 소자의 게이트 절연막은가장 일반적으로 사용되는 SiO2 (200nm)와 고분자 절연막으로 잘 알려진 poly-4-vinylphenol(PVP)를 사용하였다. 실리콘 나노와이어의 전기적 특성을 각각 SiO2무기 절연막에서의 non-embedded상태, PVP 유기 절연막에서의 embedded 상태에서 비교분석 하였다. 전기적 특성은 I-V 측정을 통하여 Ion/Ioff ratio, 이동도, subthreshold swing, threshold voltage값을 평가하였다.