• Journal of information and communication convergence engineering
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• v.14 no.4
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• pp.268-271
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• 2016

An efficient inductive switching noise suppression technique for mixed-signal integrated circuits (ICs) using standard CMOS digital technology is proposed. The proposed design technique uses a parallel RC circuit, which provides a damping path for the switching noise. The proposed design technique is used for designing a mixed-signal circuit composed of a ring oscillator, a digital output buffer, and an analog noise sensor node for $0.13-{\mu}m$ CMOS digital IC technology. Simulation results show a 47% reduction in the on-chip inductive switching noise coupling from the noisy digital to the analog blocks in the same substrate without an additional propagation delay. The increased power consumption due to the damping resistor is only 67% of that of the conventional source damping technique. This design can be widely used for any kind of analog and high frequency digital mixed-signal circuits in CMOS technology

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.5
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• pp.530-535
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• 2004

We have studied 90$^{\circ}$ twisted nematic mode switching by fringe electric field(F-TN mode) using a liquid crystal (LC) with negative dielectric anisotropy. In the device, two polarizers are parallel each other, electrodes exist only on bottom substrate, and one of rubbing direction is coincident with polarizer axis. Therefore, the cell shows a black state before a voltage is applied. With a bias voltage generating fringe-electric field, the LC twists perpendicular to fringe electric field such that the LCs are almost homogeneously aligned except near the bottom surface since the negative type of the LC is used. Consequently, the new device exhibits much wider viewing angle than that of the conventional TN mode due to in-plane switching and relatively high transmittance since the LC director above whole electrode area aligns parallel to the polarizer axis.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.403-404
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• 2012

We fabricated TFT devices with the GeSe channel. A single device consists of a Pt source and drain, a Ti glue layer and a GeSe chalcogenide channel layer on SiO2/Si substrate which worked as the gate. We confirmed the drain current with variations of gate bias and channel size. The I-V curves of the switching device are shown in Fig. 1. The channel of the device always contains amorphous state, but can be programmed into two states with different threshold voltages (Vth). In each state, the device shows a normal Ovonic switching behavior. Below Vth (OFF state), the current is low, but once the biasing voltage is greater than Vth (ON state), the current increases dramatically and the ON-OFF ratio is high. Based on the experiments, we draw the conclusion that the gate voltage can enhance the drain current, and the electric field by the drain voltage affects the amorphous-amorphous transition. The switching device always contains the amorphous state and never exhibits the Ohmic behavior of the crystalline state.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.280-281
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• 2011

We fabricated the devices of TFT type with the amorphous chalcogenide channel. A single device consists of a Pt source and drain, a Ti glue layer and a GeSe chalcogenide channel layer on SiO2/Si substrate which worked as the gate. We confirmed the drain current with variations of gate bias and channel size. The I-V curves of the switching device are shown in Fig. 1. The channel of the device always contains amorphous state, but can be programmed into two states with different threshold voltages (Vth). In each state, the device shows a normal Ovonic switching behavior. Below Vth (OFF state), the current is low, but once the biasing voltage is greater than Vth (ON state), the current increases dramatically and the ON-OFF ratio is about 4 order. Based on the experiments, we contained the conclusion that the gate voltage can enhance the drain current, and the electric field by the drain voltage affects the amorphous-amorphous transition. The switching device always contains the amorphous state and never exhibits the Ohmic behavior of the crystalline state.

• Journal of Magnetics
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• v.14 no.1
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• pp.15-17
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• 2009

The magnetostatic interaction between the two magnetic nanowires was studied by using the longitudinal magneto-optical Kerr effect (MOKE). For this purpose two magnetic nanowires having different widths (400 nm, 800 nm) were fabricated on an Si substrate with electron beam lithography and the lift-off method. Magnetic hysteresis loops measured by MOKE showed double switching behavior, corresponding to the separated switching fields of each wire. The switching field of the narrow wire was greatly affected by the separation between the two wires. Based on how the switching field changes with decreasing separation, it is concluded that the magnetostatic field of the 800-nm wire strongly affects the switching of the 400-nm wire when the separation is less than $0.5{\mu}m$.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1879-1881
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• 1999

(Ba,Sr)$TiO_3$[BST] thin films were fabricated on Pt/Ti/$SiO_2$/Si substrate by RF sputtering. We investigated the effects of substrate temperature on the structural and dielectric properties of BST thin films. Increasing the substrate temperature, barium multi titanate phases were decreased, and BST (100), (200) peaks were increased. The relative dielectric constant and dielectric loss of the BST thin films at the substrate temperature of $500^{\circ}C$ were 300 and 0.018, respectively at l[kHz]. In all films, the dielectric constants decreased. Dielectric losses increased as increasing the frequency. The switching voltage was 5V of the BST thin films at the substrate temperature of $500^{\circ}C$.

• Korean Journal of Materials Research
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• v.20 no.5
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• pp.241-245
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• 2010

One of the weak points of the Cr-doped SZO is that until now, it has only been fabricated on perovskite substrates, whereas NiO-ReRAM devices have already been deposited on Si substrates. The fabrication of RAM devices on Si substrates is important for commercialization because conventional electronics are based mainly on silicon materials. Cr-doped ReRAM will find a wide range of applications in embedded systems or conventional memory device manufacturing processes if it can be fabricated on Si substrates. For application of the commercial memory device, Cr-doped $SrZrO_3$ perovskite thin films were deposited on a $SrRuO_3$ bottom electrode/Si(100)substrate using pulsed laser deposition. XRD peaks corresponding to the (112), (004) and (132) planes of both the SZO and SRO were observed with the highest intensity along the (112) direction. The positions of the SZO grains matched those of the SRO grains. A well-controlled interface between the $SrZrO_3$:Cr perovskite and the $SrRuO_3$ bottom electrode were fabricated, so that good resistive switching behavior was observed with an on/off ratio higher than $10^2$. A pulse test showed the switching behavior of the Pt/$SrZrO_3:Cr/SrRuO^3$ device under a pulse of 10 kHz for $10^4$ cycles. The resistive switching memory devices made of the Cr-doped $SrZrO_3$ thin films deposited on Si substrates are expected to be more compatible with conventional Si-based electronics.

• Molecules and Cells
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• v.43 no.10
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• pp.841-847
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• 2020

Histone acetylation and deacetylation play central roles in the regulation of chromatin structure and transcription by RNA polymerase II (RNA Pol II). Although Hda1 histone deacetylase complex (Hda1C) is known to selectively deacetylate histone H3 and H2B to repress transcription, previous studies have suggested its potential roles in histone H4 deacetylation. Recently, we have shown that Hda1C has two distinct functions in histone deacetylation and transcription. Histone H4-specific deacetylation at highly transcribed genes negatively regulates RNA Pol II elongation and H3 deacetylation at inactive genes fine-tunes the kinetics of gene induction upon environmental changes. Here, we review the recent understandings of transcriptional regulation via histone deacetylation by Hda1C. In addition, we discuss the potential mechanisms for histone substrate switching by Hda1C, depending on transcriptional frequency and activity.

• Applied Science and Convergence Technology
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• v.26 no.5
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• pp.129-132
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• 2017

We report a chemical vapor deposition approach and optimized growth condition to the synthesis of single layer molybdenum disulfide ($MoS_2$). Obtaining large grain size with continuous $MoS_2$ atomically thin films is highly responsible to the growth distance between molybdenum trioxide source and receiving silicon substrate. Experimental results indicate that triangular shape $MoS_2$ grain size could be enlarged up to > 80um with the precisely controlled the source-to-substrate distance under 7.5 mm. Furthermore, we demonstrate fabrication of a memory device by employing poly(methyl methacrylate) (PMMA) as insulating layer. The fabricated devices have a PMMA-$MoS_2$/metal configuration and exhibit a bistable resistance switching behavior with high/low-current ratio around $10^3$.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.367-370
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• 2004

We fabricated PLT(5) thin film on $Pt/TiO_x/SiO_2/Si$ substrate by using sol-gel method and investigated leakage current, switching and retention properties. The leakage current density of PLT(5) thin film was $3.56{\times}10^{-7}A/cm^2$ at 4V. In the examination of switching properties, pulse voltage and load resistance were $2V{\~}5V$ and $50{\Omega}{\~}3.3k{\Omega}$, respectively. Switching time had a tendency to decrease from 520ns to 140ns with the increase of pulse voltage, and also the time was increased from 140ns to $13.7{\mu}s$ with the increase of load resistance. The activation energy obtained from the relation of applied pulse voltage and switching time was about 143kV/cm. The error of switched charge density between hysteresis loop and experiment of polarization switching was about $10\%$. Also, polarization in retention was decreased as much as about $8\%$ after $10^5$s.