• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.406-406
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• 2004

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.25-33
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• 2007

In this paper, a fourth-order single-bit delta-sigma modulator is presented and implemented. The loop-filter is composed of both feedback and feedforward paths. Measurement results show that maximum 99dB dynamic range is achievable at a clock rate of 3.2MHz for 20kHz baseband. The proposed modulator has been fabricated in a $0.18{\mu}m$ standard CMOS process.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.3
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• pp.33-38
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• 2002

To establish the national standard of capacitance, four main electrodes of the cross capacitor which were evaluated to linearity and roundness less the $\pm 1 \mu m$ respectively have to be adjusted symmetrically in an inner cylinder. Four LM shafts with diameter of 5 mm were installed between main electrodes of the cross capacitor, and the electrodes were adjusted, as the first step, by means of the measured capacitance. In the second step, the symmetrical adjustment up to $\pm 1.2\mu m$ was performed by using a ball sensor, ball-type movable sensor, non-contacting capacitive sensor and upper guard sensor which were developed in this project.

• Journal of Sensor Science and Technology
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• v.25 no.5
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• pp.326-332
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• 2016

A novel CMOS temperature sensor with binary output is implemented by using fully differential switched-capacitor circuits for resistorless implementation of the temperature sensor core. Temperature sensing is based on the temperature characteristics of the pn diodes implemented by substrate pnp transistors fabricated using standard CMOS processes. The binary outputs are generated by using the charge-balance principle that eliminates the division operation of the PTAT voltage by the bandgap reference voltage. The chip was designed in a MagnaChip $0.35-{\mu}m$ CMOS process, and the designed circuit was verified using Spectre circuit simulations. The verified circuit was laid out in an area of $950{\mu}m{\times}557 {\mu}m$ and is currently under fabrication.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.70-82
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• 2014

A nano-power CMOS voltage reference is proposed in this paper. Through a combination of switched-capacitor technology with the body effect in MOSFETs, the output voltage is defined as the difference between two gate-source voltages using only a single PMOS transistor operated in the subthreshold region, which has low sensitivity to the temperature and supply voltage. A low output, which breaks the threshold restriction, is produced without any subdivision of the components, and flexible trimming capability can be achieved with a composite transistor, such that the chip area is saved. The chip is implemented in $0.18{\mu}m$ standard CMOS technology. Measurements show that the output voltage is approximately 123.3 mV, the temperature coefficient is $17.6ppm/^{\circ}C$, and the line sensitivity is 0.15 %/V. When the supply voltage is 1 V, the supply current is less than 90 nA at room temperature. The area occupation is approximately $0.03mm^2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.989-998
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• 2012

A ratio type of capacitance measurement circuit is proposed to measure an extremely small value of the fF capacitance on this paper. This measurement circuit is formed with a switched-capacitor integrator, a comparator, and logic circuit blocks to control the switches. It converts the measured ratio value between the known value of on-chip capacitor and the unknown value of capacitor to the digital signal. The fF capacitance with minimized error can be obtained by calculating this ratio. This proposed circuit is designed with standard CMOS $0.18{\mu}m$ process, and various HSpice simulations prove that this capacitance measurement circuit is able to measure the capacitance under 5fF with less than ${\pm}0.3%$ error rate.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.906-909
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• 2006

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented in a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage.

• Proceedings of the KIEE Conference
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• 2001.11a
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• pp.62-64
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• 2001

In this paper, we present the fabrication and performance of tunable capacitors with various structural geometry of plates. Experimental devices have been fabricated using Cu-electroplating techniques and standard MEMS techniques. In particular, the thickness of electroplated Cu is designed below $0.5{\mu}m$ for lower actuation voltage. The fabricated tunable capacitors has been tested from $OV{\sim}42V$ and achieves a tuning ratio of $46%{\sim}64.2%$.

• Proceedings of the KIEE Conference
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• 2008.04c
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• pp.16-18
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• 2008

Several methods are proposed in the literature for losses segregation of single phase induction motor. Generally we could divide two methods for experimental determination of losses segregation for single phase induction motor. The one is relatively complicated method based on Parameter estimation of single phase induction motor. The other is simple method based on IEEE Standard 114. Segregation of losses in single phase induction motor is more complicated than that in three phase induction motor, because of the backward magnetic field component in the motor and multiplicity of different single phase type. In this paper, therefore, we studied losses segregation of capacitor-run single phase induction motor.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.3
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• pp.283-288
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• 2004

We have fabricated MIM capacitors for MMIC applications, with capacitances as high as 600pF/$\textrm{mm}^2$ and excellent electrical properties of the insulator layer. Silicon nitride thin film is the desirable material for MMIC capacitor fabrication. Standard MIM capacitance in MMIC is 300pF/$\textrm{mm}^2$ with an insulator layer thickness of more than 2000$\AA$. However, capacitors with thin insulator layers have breakdown voltages as low as 20V. We have deposited insulator layers by PECVD in our MIM structure with an air bridge between the top metal and the contact pad. The PECVD process was optimized for fabricating the desired capacitors to be used in MMIC. Silicon nitride(Si$_{x}$N$_{y}$) thin films of about 1000$\AA$ thick show capacitances of about 600pF/$\textrm{mm}^2$, and breakdown voltages above 70V at 100nA.A.A.