• Title/Summary/Keyword: stacked

Search Result 1,138, Processing Time 0.028 seconds

Selective Epitaxy Growth of Multiple-Stacked InP/InGaAs on the Planar Type by Chemical Beam Epitaxy (화학적 빔 에피탁시에 의한 평면구조에서의 InP/InGaAs 다층구조의 선택적 영역 에피 성장)

  • Han, Il-Ki;Lee, Jung-Il
    • Journal of the Korean Vacuum Society
    • /
    • v.18 no.6
    • /
    • pp.468-473
    • /
    • 2009
  • Selective area epitaxy of multiple-stacked InP/InGaAs structures were grown by chemical beam epitaxy. The width of top of the multiple-stacked InP/InGaAs layer which were selectively grown on the stripe lines parallel to the <011> direction was narrowed, while the width of top of the multiple-stacked InP/InGaAs layer on the stripe lines parallel to the <01-1> was widen. This difference according to the <011> and <01-1> direction was explained by the growth of InGaAs <311>A and B faces on the (100) InP surface on the stripe lines parallel to the <01-1> direction. Under growth rate of $1\;{\mu}m/h$, top of the multiple-stacked InP/InGaAs was flattened as the pressure of group V gas was decreased. This phenomenon was understood by the saturation of group V element on the surface.

A Design of X-Band Microstrip Array Antenna (X대역 마이크로스트립 배열 안테나)

  • Kim, Min-Joon;Cheon, I-Hwan;Kim, Ju-Hyun
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.13 no.5
    • /
    • pp.860-867
    • /
    • 2009
  • In this paper, we designed the array antenna for FMCW radar in X - band frequency, and we chose stacked structure for improvement of narrow bandwidth. The array antenna is implemented on the circuit board which is relative permittivity 2.33 and the stacked patchs are designed on the circuit board which is relative permittivity 4.6. A Foam which has a similar permittivity of air is added to keep the particular gap between array antenna and the stacked patch. The result of array antenna has characteristics that a half-power beam width is $10.6^{\circ}$ and antenna gain is 18.70 dBi and bandwidth is 1.25GHz at the design frequency of 9GHz. The result of the array antenna with the stacked structure has that the half power beam width is $15.17^{\circ}$ and the antenna gain is 15.85dBi and bandwidth is 2GHz. It is needed to improve the antenna gain as keeping bandwidth in same level.

Analysis of Stacked and Multi-layer Graphene fot the Fabrication of LEDs

  • Kim, Gi-Yeong;Min, Jeong-Hong;Jang, So-Yeong;Lee, Jun-Yeop;Park, Mun-Do;Kim, Seung-Hwan;Jeon, Seong-Ran;Song, Yeong-Ho;Lee, Dong-Seon
    • Proceedings of the Korean Vacuum Society Conference
    • /
    • 2014.02a
    • /
    • pp.433.1-433.1
    • /
    • 2014
  • The research of graphene, a monolayer of carbon atoms with honeycomb lattice structure, has explosively increased after appeared in 2004. As a result, its high transmittance, mobility, thermal conductivity, and outstanding mechanical and chemical stability have been proved. Especially, many researches were executed about the field of transparent electrode highlighting material of substituting the indium tin oxide (ITO). In addition, qualitative and quantitative improvements have been achieved due to many synthesis methods were discovered. Among them, mostly used method is chemical vapour deposition of graphene grown on copper or nickel. The transmittance, mobility, sheet resistance, and other many properties are completely changed according to these two types of synthesis method of graphene. In this research, considering the difference of characteristics as the synthesis method of graphene, what types of graphene should be used and how to use it were studied. The stacked graphene harvested on copper and multi-layer graphene harvested on nickel were compared and analyzed, as a result, the transmittance of 90% and the sheet resistance of $70{\Omega}{\square}$ was showed even though stacked graphene layers were 4 layers. The reason that could bring these results is lowered sheet resistance due to stacked monolayer graphenes. Moreover, light output power of the three stacked graphene spreading layer shows the highest value, but light-emitting diode with multi-layer graphene died out from 12mA due to also its high sheet resistance. Therefore, we need to clarify about what types of graphene and how to use the graphene in use.

  • PDF

A Study on ESD Robustness of Output Drivers for ESD Design Window Engineering (ESD 설계 마진을 위한 출력드라이버 ESD 내성 연구)

  • Kim, Jung-Dong;Lee, Gee-Du;Choi, Yoon-Chul;Kwon, Kee-Won;Chun, Jung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.48 no.12
    • /
    • pp.31-36
    • /
    • 2011
  • This paper investigates the ESD robustness of the stacked output driver with a 0.13um CMOS process. To represent an actual I/O system, we implemented stacked output driver circuits with pre-drivers and a rail-based power clamp. We implemented eight kinds of circuits varying pre-driver input connections and stacked driver size. The test circuits are examined with TLP measurements. It is shown that breakdown current and voltage can be increased by connecting the pre-driver input to a power supply and using stacked devices of a similar size. Based on the test results, design guideline is suggested to improve ESD robustness of the stacked output drivers.

A Design of Dual-band Stacked Helix Monopole Antenna with Parasitic Patch (기생 패치를 이용한 이중 대역 적층형 헬릭스 모노폴 안테나 설계)

  • Jung, Jin-Woo;Kim, Kyoung-Keun;Lee, Hyeon-Jin;Lim, Yeong-Seog
    • Journal of the Institute of Electronics Engineers of Korea TC
    • /
    • v.44 no.1
    • /
    • pp.155-161
    • /
    • 2007
  • This paper presents the design simulation, implementation, and measurement of a miniaturized PCS / Satellite DMB dual-band stacked mompole antenna with a parasitic patch for mobile communication terminals. A stacked helix is realized by using a via hole with height of 0.4 mm and a diameter of 0.35 mm to connect upper- and lower-layer helix sections for a reduction of the dimensions of the antenna. In addition the stacked helix chip antenna is interleaved with a parasitic patch to achieve two different radiation modes. The ratio of the first frequency and the second frequency vary with the geometrical parameter of the parasitic patch. The fabricated antenna uses FR-4 substrate with a relative permittivity of 4.2. Its dimensions are $15.5{\times}7.6{\times}0.4 mm^3$. The measured impedance bandwidths (VSWR<2) are 240 and 250 MHz at the operating frequencies, respectively.

GHz EMI Characteristics of 3D Stacked Chip PDN with Through Silicon Via (TSV) Connections

  • Pak, Jun-So;Cho, Jong-Hyun;Kim, Joo-Hee;Kim, Ki-Young;Kim, Hee-Gon;Lee, Jun-Ho;Lee, Hyung-Dong;Park, Kun-Woo;Kim, Joung-Ho
    • Journal of electromagnetic engineering and science
    • /
    • v.11 no.4
    • /
    • pp.282-289
    • /
    • 2011
  • GHz electromagnetic interference (EMI) characteristics are analyzed for a 3dimensional (3D) stacked chip power distribution network (PDN) with through silicon via (TSV) connections. The EMI problem is mostly raised by P/G (power/ground) noise due to high switching current magnitudes and high PDN impedances. The 3D stacked chip PDN is decomposed into P/G TSVs and vertically stacked capacitive chip PDNs. The TSV inductances combine with the chip PDN capacitances produce resonances and increase the PDN impedance level in the GHz frequency range. These effects depend on stacking configurations and P/G TSV designs and are analyzed using the P/G TSV model and chip PDN model. When a small size chip PDN and a large size chip PDN are stacked, the small one's impedance is more seriously affected by TSV effects and shows higher levels. As a P/G TSV location is moved to a corner of the chip PDNs, larger PDN impedances appear. When P/G TSV numbers are enlarged, the TSV effects push the resonances to a higher frequency range. As a small size chip PDN is located closer to the center of a large size chip PDN, the TSV effects are enhanced.

Stacked Sparse Autoencoder-DeepCNN Model Trained on CICIDS2017 Dataset for Network Intrusion Detection (네트워크 침입 탐지를 위해 CICIDS2017 데이터셋으로 학습한 Stacked Sparse Autoencoder-DeepCNN 모델)

  • Lee, Jong-Hwa;Kim, Jong-Wouk;Choi, Mi-Jung
    • KNOM Review
    • /
    • v.24 no.2
    • /
    • pp.24-34
    • /
    • 2021
  • Service providers using edge computing provide a high level of service. As a result, devices store important information in inner storage and have become a target of the latest cyberattacks, which are more difficult to detect. Although experts use a security system such as intrusion detection systems, the existing intrusion systems have low detection accuracy. Therefore, in this paper, we proposed a machine learning model for more accurate intrusion detections of devices in edge computing. The proposed model is a hybrid model that combines a stacked sparse autoencoder (SSAE) and a convolutional neural network (CNN) to extract important feature vectors from the input data using sparsity constraints. To find the optimal model, we compared and analyzed the performance as adjusting the sparsity coefficient of SSAE. As a result, the model showed the highest accuracy as a 96.9% using the sparsity constraints. Therefore, the model showed the highest performance when model trains only important features.

Post Silicon Management of On-Package Variation Induced 3D Clock Skew

  • Kim, Tak-Yung;Kim, Tae-Whan
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.12 no.2
    • /
    • pp.139-149
    • /
    • 2012
  • A 3D stacked IC is made by multiple dies (possibly) with heterogeneous process technologies. Therefore, die-to-die variation in 2D chips renders on-package variation (OPV) in a 3D chip. In spite of the different variation effect in 3D chips, generally, 3D die stacking can produce high yield due to the smaller individual die area and the averaging effect of variation on data path. However, 3D clock network can experience unintended huge clock skew due to the different clock propagation routes on multiple stacked dies. In this paper, we analyze the on-package variation effect on 3D clock networks and show the necessity of a post silicon management method such as body biasing technique for the OPV induced 3D clock skew control in 3D stacked IC designs. Then, we present a parametric yield improvement method to mitigate the OPV induced 3D clock skew.

Large Area Bernal Stacked Bilayer Graphene Grown by Multi Heating Zone Low Pressure Chemical Vapor Deposition

  • Han, Jaehyun;Yeo, Jong-Souk
    • Proceedings of the Korean Vacuum Society Conference
    • /
    • 2015.08a
    • /
    • pp.239.2-239.2
    • /
    • 2015
  • Graphene is a most interesting material due to its unique and outstanding properties. However, semi-metallic properties of graphene along with zero bandgap energy structure limit further application to optoelectronic devices. Recently, many researchers have shown that band gap can be induced in the Bernal stacked bilayer graphene. Several methods have been used for the controlled growth of the Bernal staked bilayer graphene, but it is still challenging to control the growth process. In this paper, we synthesize the large area Bernal stacked bilayer graphene using multi heating zone low pressure chemical vapor deposition (LPCVD). The synthesized bilayer graphenes are characterized by Raman spectroscopy, optical microscope (OM), scanning electron microscopy (SEM). High resolution transmission electron microscopy (HRTEM) is used for the observation of atomic resolution image of the graphene layers.

  • PDF

Magnetization Loss Characteristic of a Stacked Bi-2223 Conductor (적층 Bi-2223도체의 자화손실 특성)

  • 한형주;류경우;성기철
    • Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
    • /
    • 2002.02a
    • /
    • pp.46-49
    • /
    • 2002
  • The ac loss is an important issue in the design of superconducting cables and transformers. In these devices the Bi-2223 tapes are usually placed face-to-face In such arrangements ac loss is influenced by adjacent tapes. The effect is investigated by measuring the magnetization loss in the stacked conductor, which consists of various numbers of Bi-2223 tapes. For the stacked conductor in perpendicular field the magnetization loss at low fields is greatly decreased, compared to the loss of the single tape. The loss at high fields is unaffected. This behavior is well described by the slab model.

  • PDF