• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.114-121
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• 2001

A circuit model for active-controlled field emitter array(ACFEA) as an electron source of active-controlled field emission display(ACFED) has been proposed. The ACFEA with hydrogenated amorphous silicon thin-film transistor(a-Si:H TFT) and Spindt-type molibdenum tips (Spindt-Mo FEA) has been fabricated monolithically on the same glass. A-Si:H TFT is used as a control device of field emitters, resulting in stabilizing emission current and lowering driving voltage. The basic model parameters extracted from the electrical characteristics of the fabricated a-Si:H TFT and Spindt-Mo FEA were implemented into the ACFEA model with a circuit simulator SPICE. The accuracy of the equivalent circuit model was verified by comparing the simulated results with the measured one through DC analysis of the ACFEA. The transient analysis of the ACFEA showed that the gate capacitance of FEA along with the drivability of TFT strongly affected the response time. With the fabricated ACFEA, we obtained a response time of 15$mutextrm{s}$, which was enough to make 4bit/color gray scale with the pulse width modulation (PWM).

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.47-56
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• 1999

As the density of logic gates of VLSI chips has rapidly increased, more number of I/O pins has been required. This results in bigger package size and higher packager cost. The package cost is higher than the cost of bare chips for high I/O count VLSI chips. As the density of logic gates increases, the reduction method of the number of I/O pins for a given complexity of logic gates is required. In this paper, we propose the novel I/O interface circuit using CTR (Constant-Transition-Rate) code to reduce 50% of the number of I/O pins. The rising and falling edges of the symbol pulse of CTR codes contain 2-bit digital data, respectively. Since each symbol of the proposed CTR codes contains 4-bit digital data, the symbol rate can be reduced by the factor of 2 compared with the conventional I/O interface circuit. Also, the simultaneous switching noise(SSN) can be reduced because the transition rate is constant and the transition point of the symbols is widely distributed. The channel encoder is implemented only logic circuits and the circuit of the channel decoder is designed using the over-sampling method. The proper operation of the designed I/O interface circuit was verified using. HSPICE simulation with 0.6 m CMOS SPICE parameters. The simulation results indicate that the data transmission rate of the proposed circuit using 0.6 m CMOS technology is more than 200 Mbps/pin. We implemented the proposed circuit using Altera's FPGA and confimed the operation with the data transfer rate of 22.5 Mbps/pin.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.33-46
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• 2015

In this paper, we predicts the analog and digital circuit performance of FinFETs that are scaled down following the ITRS(International technology roadmap for semiconductors). For accurate prediction of the circuit performance of scaled down devices, accurate parasitic resistance and capacitance analytical models are developed and their accuracies are within 2 % compared to 3D TCAD simulation results. The parasitic capacitance models are developed using conformal mapping, and the parasitic resistance models are enhanced to include the fin extension length($L_{ext}$) with respect to the default parasitic resistance model of BSIM-CMG. A new algorithm is developed to fit the DC characteristics of BSIM-CMG to the reference DC data. The proposed capacitance and resistance models are implemented inside BSIM-CMG to replace the default parasitic model, and SPICE simulations are performed to predict circuit performances such as $f_T$, $f_{MAX}$, ring oscillators and common source amplifier. Using the proposed parasitic capacitance and resistance model, the device and circuit performances are quantitatively predicted down to 5 nm FinFET transistors. As the FinFET technology scales, due to the improvement in both DC characteristics and the parasitic elements, the circuit performance will improve.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.6
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• pp.85-96
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• 2000

It is necessary that fully differential operational amplifier circuit should drive an external load in the VLSI design such as SCF(Switched Capacitor Filter), D/A Converter, A/D Converter, Telecommunication Circuit and etc. The conventional CMOS operational amplifier circuit has many problems according to CMOS technique. Firstly, Capacity of large loads are not able to operate well. The problem can be solve to use class AB stages. But large loads are operate a difficult, because an element of existing CMOS has a quadratic functional relation with input and output voltage versus output current. Secondly, Whole circuit of dynamic range decrease, because a range of input and output voltages go down according as increasing of intergration rate drop supply voltage. The problem can be improved by employing fully differential operational amplifier using differential output stage with wide output swing. In this paper, we proposed new current mirror has large output impedance and good current matching with input an output current and compared with characteristics for operational amplifier using cascoded current mirror. To obtain large output swing and low power consumption we suggest a fully differential operational amplifier. The circuit employs an output stage composed new current mirror and two amplifier stage. The proposed circuit is layout and circuit of capability is inspected through simulation program(SPICE3f).

• Journal of Sensor Science and Technology
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• v.12 no.6
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• pp.231-240
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• 2003

The problem of power consumption and the limitation of a chip area should be considered when the pixel number of the edge detection circuit increases to fabricate a vision chip for edge detection with high resolution. The numeric increment of the unit circuit causes power consumption to increase and require a larger chip area. An increment of power consumption and a limitation of chip area with several ten milli-meters square supplied by the CMOS foundry company restrict the pixel numbers of the edge detection circuit. In this paper, we proposed a electronic switch to minimize the power consumption owing to the numeric increment of the edge detection circuit to realize a vision chip for edge detection with high resolution. We also applied a method by which photodetector and edge detection circuit are separated to implement a vision chip with a higher resolution. The photodetector circuit with $128{\times}128$ pixels uses a common edge detection circuit with $1{\times}128$ pixels so that resolution was improved at the same chip area. The chip size is $4mm{\times}4mm$ and the power consumption was confirmed to be about 20mW using SPICE.

• 전자공학회논문지 IE
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• v.49 no.1
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• pp.18-23
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• 2012

In this paper, a potable device application for DC-DC converter was designed for voltage protection circuit. Voltage protection circuit to offer the under voltage lock out and over voltage protection consists of a comparator and bais circuits were implemented using. XFAB 1um CMOS process, SPICE simulations was confirmed through the characteristics. Simulation results, under voltage lock out input voltage is 4.8 V higher when the turn-on and, 4.2 V less when turn-off. When the input voltage is low voltage is applied can be used to prevent malfunction of the circuit. Over voltage protection is 3.8 V reference voltage when the output voltage caused by blocking circuit prevents device destruction can be used to improve the stability and reliability. The virtual control circuits of the DC-DC converter connected. According to the results of the abnormal voltage, voltage protection circuit behavior was confirmed. The proposed voltage protection circuit of the DC-DC converter cell is useful are considered.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.85-93
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• 2007

This paper presents new LVDS I/O circuits with a high noise margin for use in highly parallel I/O environments. The proposed LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and a output stage with common mode feedback(CMFB). The differential phase splitter generates a pair of differential signals which have a balanced duty cycle and $180^{\circ}$ phase difference over a wide supply voltage variation due to SSO(simultaneous switching output) noises. The CMFB output stage produces the required constant output current and maintains the required VCM(common mode voltage) within ${\pm}$0.1V tolerance without external circuits in a SSO environment. The proposed receiver circuits in this paper utilizes a three-stage structure(single-ended differential amp., common source amp., output stage) to accurately receive high-speed signals. The receiver part employs a very wide common mode input range differential amplifier(VCDA). As a result, the receiver improves the immunities for the common mode noise and for the supply voltage difference, represented by Vgdp, between the transmitter and receiver sides. Also, the receiver produces a rail-to-rail, full swing output voltage with a balanced duty cycle(50% ${\pm}$ 3%) without external circuits in a SSO environment, which enables correct data recovery. The proposed LVDS I/O circuits have been designed and simulated with 0.18um TSMC library using H-SPICE.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.8
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• pp.719-729
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• 2000

Prefetching aims at reducing memory latency by fetching, in advance, data that are likely to be requested by the processor in a near future. The effectiveness of prefetching is determined by how accurate the prediction on the needed instructions and data is. Most previous studies on prefetching were limited to proposing a particular prefetch scheme and its performance evaluation, paying little attention to theoretical aspects of prefetching. This paper focuses on the theoretical aspects of instruction prefetching. For this purpose, we propose a clairvoyant prefetch model that makes use of perfect history information. Based on this theoretical model, we analyzed upper limits on the prefetch prediction accuracies of the SPEC benchmarks. The results show that the prefetch prediction accuracy is very high when there is no cache. However, as the size of the instruction cache increases, the prefetch prediction accuracy drops drastically. For example, in the case of the spice benchmark, the prefetch prediction accuracy drops from 53% to 39% when the cache size increases from 2Kbyte to 16Kbyte (assuming 16byte block size). These results indicate that as the cache size increases, most localities are captured by the cache and that instruction prefetching based on the information extracted from the references that missed in the cache suffers from prediction inaccuracies

• Journal of Internet Computing and Services
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• v.10 no.5
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• pp.195-209
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• 2009

The embedded software has been become more important than the hardware in mobile systems in ubiquitous society. The improvement models such as CMMI(Capability Maturity Model Integration) and SPICE(Software Process Improvement and Capability dEtermination) are used to improve the quality of software in general systems. Software process improvement is also necessary for mobile embedded software development to improve its quality. It is not easy to apply the general software improvement model to the mobile embedded software development due to the high cost effectiveness and heavy process. On the other hand, XP has the characteristics on focused communications with customers and iteration development. It is specially suitable for mobile embedded software development as depending on customer's frequent requirement changes and hardware attributes. In this paper, we propose a framework for development small process improvement based XP(eXtreme Programming)'s practice in order to accomplish CMMI level 2 or 3 in mobile embedded software development at the small organizations. We design and implement the Mobile Embedded Software Process Improvement System(MESPIS) to support process improvement. We also suggest the evaluation method for the mobile embedded software development process improvement framework with CMMI coverage check by comparing other process improvement model. In the future, we need to apply this proposed framework to real project for practical effectiveness and the real cases quantitative. It also include the enhance the functionality of MESPIS.

• Korean Journal of Food Science and Technology
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• v.46 no.2
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• pp.256-261
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• 2014

This study was conducted to determine the effect of gamma-ray and electron-beam irradiation on dried spices (black pepper, red pepper, parsley, and basil) using the photostimulated luminescence (PSL), thermoluminescence (TL) and electron spin resonance (ESR) methods. The spices were irradiated at 0, 1, 5, and 10 kGy. All non-irradiated spices had photon counts (PCs) less than 700 PCs. The PCs of three irradiated spices (red pepper, parsley, and basil) were clearly distinguishable from those of non-irradiated ones, exhibiting PSL signals higher than 5000 PCs. However, negative PSL counts (<700 PCs) were obtained for most irradiated black pepper, except those irradiated with 5 kGy gamma rays and 10 kGy electron-beams. TL glow curves of the irradiated spices showed a higher peak at $150-250^{\circ}C$. TL ratios were found to be less than 0.1 for non-irradiated spices and higher than 0.1 for irradiated ones. No ESR signal was observed for any irradiated spice except red pepper, which displayed cellulose-based ESR spectra. Therefore, the results suggest that the PSL, TL, and ESR methods are effective detection techniques for dried spices irradiated with electron beams as well as gamma rays.