• Geosystem Engineering
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• v.21 no.6
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• pp.297-308
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• 2018

In this paper, we investigate the differences between LNG price of South Korea and Japan. Although S. Korean and Japanese LNG markets have similar structures, there are some differences in the price formation. From DCC-MGARCH, we confirm that Japan LNG price have less persistence of disturbance on time than S. Korean LNG price. The conditional correlation also shows linkage effects between LNG prices and impacts of S-curve and DS-curve. Moreover, ARDL estimation result shows that there is co-integration in all models and that impacts of Fukushima accident and LNG volumes are responsible for the increase in Japanese LNG price. Also, adjustment speed of error correction term shows that Japan's deviation from long-run equilibrium disappears faster than S. Korea does, indicating relatively strong Japanese linkage between LNG price and oil price.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.981-984
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• 2009

In this paper, We design RS(255,239) decoder with modified Euclidean algorithm, which show polynomic coefficient state machine instead of calculating coefficients of modified Euclidean algorithm. This design can reduce complexity and implement High-speed Read Solomon decoder. Additionally, we have synthesized with Xilinx XC4VLX60. From synthesis, it can operate at clock frequency of 77.4MHz, and gate count is 20,710.

• Journal of Semiconductor Engineering
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• v.2 no.1
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• pp.99-108
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• 2021

Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC) seem to become the hottest ADC architecture during the past decade in implementing energy-efficient high performance ADCs. In this overview, we will review what kind of circuit techniques and architectural advances have contributed to place the SAR ADC architecture at its current position, beginning from a single SAR ADC and moving to various hybrid architectures. At the end of this overview, a recently reported compact and high-speed SAR-Flash ADC is introduced as one design example of SAR-based hybrid ADC architecture.

• Atmosphere
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• v.22 no.1
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• pp.1-12
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• 2012

The Atmospheric motion vectors (AMVs) derived using infrared (IR) channel imagery of geostationary satellites have been utilized widely for real-time weather analysis and data assimilation into global numerical prediction model. As the horizontal resolution of sensors on-board satellites gets higher, it becomes possible to identify atmospheric motions induced by convective clouds ($meso-{\beta}$ and $meso-{\gamma}$ scales). The National Institute of Meteorological Research (NIMR) developed the high resolution visible (HRV) AMV algorithm to detect mesoscale atmospheric motions including ageostrophic flows. To retrieve atmospheric motions smaller than $meso-{\beta}$ scale effectively, the target size is reduced and the visible channel imagery of geostationary satellite with 1 km resolution is used. For the accurate AMVs, optimal conditions are decided by investigating sensitivity of algorithm to target selection and correction method of height assignment. The results show that the optimal conditions are target size of 32 km ${\times}$ 32 km, the grid interval as same as target size, and the optimal target selection method. The HRV AMVs derived with these conditions depict more effectively tropical cyclone OMAIS than IR AMVs and the mean speed of HRV AMVs in OMAIS is slightly faster than that of IR AMVs. Optimized mesoscale AMVs are derived for 6 months (Feb. 2010-Jun. 2010) and validated with radiosonde observations, which indicates NIMR's HRV AMV algorithm can retrieve successfully mesoscale atmospheric motions.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.3
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• pp.206-212
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• 2017

Induction motor torque is the reactive power is needed which corresponds to the exciting current to generate the magnetic flux as the product of current and flux. For use in the method of supplying the required reactive power to the induction motor power factor correction apparatus using a lot of ways to supply in place of the power supply side, when using a power factor compensation device can reduce the apparent power, the power factor can be improved. However, the distance to the emergency generator transformers or motors from the motor capacity is smaller but short and difficult to maneuver the theory and practice of the operating characteristics of the starting characteristics of the motor used a lot of large industrial plants were measured and analyzed. Therefore, this study investigated the motor starting Analysis and interpretation for the relationship with the large motor starting torque and speed during motor starting.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.43 no.5
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• pp.405-412
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• 2015

This paper represents a filter design to estimate the airspeed of a spin-stabilized, trajectory-correctible artillery ammunition. Due to the limited power and space in operational point of view, the airspeed sensor is not installed, and thus the airspeed need to be estimated using limited sensor measurements. The only IMU measurements(three-axis specific forces and angular rates) are used in this application. The extended Kalman filter algorithm is applied since a linear filter can not cover the its wide operational range in airspeed and altitude. In the implementation of the EKF, the state and measurement equations are transformed into the no-roll frame for simple form of Jacobian matrix. The simulation study is conducted to evaluate the performance of the filter under various environment conditions of sensor noise and wind turbulence. In addition, the effect of the choice in filter design parameters, i.e. process error covariance matrices is analyzed on the performance of the estimation of airspeed and angular rates.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.3
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• pp.214-222
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• 2015

The superiority of gallium nitride FET (GaN FET) over silicon MOSFET is examined in this paper. One of the outstanding features of GaN FET is low reverse-recovery charge, which enables continuous conduction mode operation of totem-pole bridgeless boost power factor correction (PFC) circuit. Among many bridgeless topologies, totem-pole bridgeless shows high efficiency and low conducted electromagnetic interference performance, with low cost and simple control scheme. The operation principle, control scheme, and circuit implementation of the proposed topology are provided. The converter is driven in two-module interleaved topology to operate at a power level of 5.5 kW, whereas phase-shedding control is adopted for light load efficiency improvement. Negative bias circuit is used in gate drivers to avoid the shoot-through induced by high speed switching. The superiority of GaN FET is verified by constructing a 5.5 kW prototype of two-module interleaved totem-pole bridgeless boost PFC converter. The experiment results show the highest efficiency of 98.7% at 1.6 kW load and an efficiency of 97.7% at the rated load.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.29-34
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• 2005

This paper describes a novel internal clock generator, called duty cycle-corrected analog synchronous mirror delay (DCC-ASMD). The proposed circuit is well suited for dual edge-triggered systems such as double data-rate synchronous DRAM since it can achieve clock synchronization within two clock cycles with accurate duty cycle correction. To evaluate the performance of the proposed circuit, DCC-ASMD was designed using a $0.35\mu$m CMOS process technology. Simulation results show that the proposed circuit generates an internal clock having $50\%$ duty ratio within two clock cycles from the external clock having duty ratio range of $40\;\~\;60$.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.12
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• pp.1028-1036
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• 2014

A design procedure is established for hypersonic nozzles by using MOC(Method of Characteristics) and CFD. The inviscid nozzle contour is designed by MOC, then BLC(Boundary Layer Correction) is made by evaluating the boundary layer thickness from viscous CFD analysis. By comparing various definitions of the boundary layer thicknesses, it seems that the boundary layer thickness of 95% speed of the maximum value at the cross section satisfies best the design Mach number. Design procedure is as follow; MOC design, grid generation, inviscid analysis, viscous analysis, BLC and viscous analysis for confirmation and post-processing. All procedures are made automatically by using the batch processing.

• Transactions of the Society of Information Storage Systems
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• v.1 no.2
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• pp.155-160
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• 2005

In this paper, the channel decoder promising reliable data retrieving in noisy holographic channel has been developed for holographic WORM(write once read many) system. It covers various DSP(digital signal processing) blocks, such as align mark detector, adaptive channel equalizer, modulation decoder and ECC(error correction code) decoder. The specific schemes of DSP are designed to reduce the effect of noises in holographic WORM(H-WORM) system, particularly in prototype of DAEWOO electronics(DEPROTO). For real time data retrieving, the channel decoder is redesigned for FPGA(field programmable gate array) based hardware, where DSP blocks calculate in parallel sense with memory buffers between blocks and controllers for driving peripherals of FPGA. As an input source of the experiments, MPEG2 TS(transport stream) data was used and recorded to DEPROTO system. During retrieving, the CCD(charge coupled device), capturing device of DEPROTO, detects retrieved images and transmits signals of them to the FPGA of hardware channel decoder. Finally, the output data stream of the channel decoder was transferred to the MPEG decoding board for monitoring video signals. The experimental results showed the error corrected BER(bit error rate) of less than $10^{-9}$, from the raw BER of DEPROTO, about $10^{-3}$. With the developed hardware channel decoder, the real-time video demonstration was possible during the experiments. The operating clock of the FPGA was 60 MHz, of which speed was capable of decoding up to 120 mega channel bits per sec.