• Journal of information and communication convergence engineering
• /
• v.19 no.3
• /
• pp.175-179
• /
• 2021

Enhancing the reliability of the system is important for recent system-on-chip (SoC) designs. This importance has led to studies on fault diagnosis and tolerance. Fault-injection (FI) techniques are widely used to measure the fault-tolerance capabilities of resilient systems. FI techniques suffer from limitations in relation to environmental conditions and system features. Moreover, a hardware-based FI can cause permanent damage to the target system, because the actual circuit cannot be restored. Accordingly, we propose a simulation-based FI framework based on the Verilog Procedural Interface for measuring the failure rates of SoCs caused by soft errors. We execute five benchmark programs using an ARM Cortex M0 processor and inject soft errors using the proposed framework. The experiment has a 95% confidence level with a ±2.53% error, and confirms the reliability and feasibility of using proposed framework for fault analysis in SoCs.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.12 no.2
• /
• pp.35-41
• /
• 2012

Due to the technology scaling, more transistors can be placed on a cache memories of a processor. However, processors become more vulnerable to the soft error because of the highly integrated transistors, and consequently, the reliability of the cache memory must consider seriously at the design space level. In this paper, we propose the reliability improving technique which can be achieved with low energy and low area overheads. The simulation experiments of the proposed scheme shows over 95.4% of protection rate against the soft error with only 0.26% of performance degradations. Also, It requires only 2.96% of extra energy consumption.

• Journal of Satellite, Information and Communications
• /
• v.10 no.1
• /
• pp.22-28
• /
• 2015

In this paper, we propose a new computationally efficient joint iterative multi-input multi-output (MIMO) detection scheme using a soft interference cancellation and minimum mean squared-error (SIC-MMSE) method. The critical computational burden of the SIC-MMSE scheme lies in the multiple inverse operations of the complex matrices. We find a new way which requires only a single matrix inversion by utilizing the Taylor series expansion of the matrix, and thus the computational complexity can be reduced. The computational complexity reduction increases as the number of antennas is increased. The simulation results show that our method produces almost the same performances as the conventional SIC-MMSE with reduced computational complexity.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.55 no.3
• /
• pp.111-115
• /
• 2006

We investigated accelerated soft error rate(ASER) in 8M static random access memory(SRAM) cells. The effects on ASER by well structure, operational voltage, and cell transistor threshold voltage are examined. The ASER decreased exponentially with respect to operational voltage. The chips with buried nwell1 layer showed lower ASER than those either with normal well structure or with buried nwell1 + buried pwell structure. The ASER decreased as the ion implantation energy onto buried nwell1 changed from 1.5 MeV to 1.0 MeV. The lower viscosity of the capping layer also revealed lower ASER value. The decrease in the threshold voltage of driver or load transistor in SRAM cells caused the increase in the transistor on-current, resulting in lower ASER value. We confirmed that in order to obtain low ASER SRAM cells, it is necessary to also the buried nwell1 structure scheme and to fabricate the cell transistors with low threshold voltage and high on-current.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.55 no.4
• /
• pp.199-203
• /
• 2006

This paper presents an ASER (Accelerated Soft Error Rate) integral model. The model is based on the facts that the generated EHP/s(electron hole pairs) are diminished after some residual range of the incident alpha particle, where residual range is a function of the incident angle and the capping layer thickness over the semiconductor junction. The ASER is influenced by the flux of the alpha particles, the junction area ratio, the alpha particle incident angle when the critical charge is same as the collected charge, and the sizes of the alpha source and the chip. The model was examined with 8M static RAM samples. The measured ASER data showed good agreement with the calculated values using the model. The ASER decreased exponentially with respect to the operational voltage. As the capping layer thickness increases up to $16{\mu}m$, the ASER increases, and after that thickness, the ASER decreases. The ASER increased as the depth of BNW increased from $0{\mu}m\;to\;4{\mu}m$. and then saturated. The ASER decreased as the node capacitance increased from 2fF to 5fF.

• Journal of the Ergonomics Society of Korea
• /
• v.32 no.1
• /
• pp.87-96
• /
• 2013

Objective: The aim of this study is to describe several issues which should be considered in the human reliability analysis of soft control operations in nuclear power plants. Background: The operational environment of advanced main control rooms is totally different from that of conventional control rooms. The soft control is one of the major distinguishable features of the advanced main control rooms. The soft control operations should be analyzed to estimate the effects on human reliability. Method: The literatures, about task analysis, simulation data analysis, and a human reliability analysis method for the soft control, were reviewed. From the review, important issues for the human reliability analysis of the soft control were raised. Results: The results of task and simulation data analysis showed that the soft control characteristics could have large effect on human reliability and they should be considered in the human reliability analysis of the soft control operations. Conclusion: The soft control may affect human error and performance of operators. The issues described in this paper should be considered in the human reliability method for the advanced main control rooms. Application: The results of the soft control operation analysis might help to design more efficient interface and education/training program for preventing human errors. The described issues might help to develop a human reliability analysis method for soft control operations.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.11 no.4
• /
• pp.1954-1971
• /
• 2017

In this work, first, a multiuser detection (MUD) algorithm based on component-level soft interference cancellation and linear minimum mean square error (CLSIC-LMMSE) is proposed, which can enhance the bit error ratio (BER) performance of the traditional SIC-LMMSE-based MUD by mitigating error propagation. Second, for non-binary low density parity check (NB-LDPC) coded high-order modulation systems, when the proposed algorithm is integrated with partial mapping, the receiver with iterative detection and decoding (IDD) achieves not only better BER performance but also significantly computational complexity reduction over the traditional SIC-LMMSE-based IDD scheme. Extrinsic information transfer chart (EXIT) analysis and numerical simulations are both used to support the conclusions.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.2
• /
• pp.32-39
• /
• 1996

Hybrid decision decoding for the extended hamming codes without retransmission, which is a combination of hard and soft decision decoding, is proposed and its performance is analyzed in this paper. As results, hybsrid decision decoding shows a little bit higher residual bit error rate than soft decision decoding. However, as the size of the extended hamming code increases, the difference of th enumber of comparisons increases further. In addition, hybrid decision decoding shows almost same residual bit error rate as hard decision decoding with retrassmission and shows much lower residual bit error rate than hard decision decoding without retransmission.

• The Korean Journal of Applied Statistics
• /
• v.17 no.1
• /
• pp.75-88
• /
• 2004

The Support Vector Machine(SVM) algorithm has paid attention on maximizing the shortest distance between sample points and discrimination hyperplane. This paper suggests the total margin algorithm which considers the distance between all data points and the separating hyperplane. The method extends existing support vector machine algorithm. In addition, this newly proposed method improves the generalization error bound. Numerical experiments show that the total margin algorithm provides good performance, comparing with the previous methods.

• Journal of IKEEE
• /
• v.27 no.4
• /
• pp.683-686
• /
• 2023

In this paper, we designed a Delayed Dual Core Lock-Step (D-DCLS) processor where two cores operate same instructions with delay and the result is compared to mitigate soft errors and common mode failures in automotive electronic systems. Because D-DCLS does not know which core an error occurred in, each core must be recovered to the point before the error occurred, but complex hardware modifications are required to return all intermediate values on the pipeline stage. In this paper, in order for easy hardware implementation, all register values are saved to a buffer whenever a branch instruction is executed. When an error is detected, the saved register values are automatically restored, and then 'BX LR' instruction is executed to return to the last branch point. The proposed D-DCLS processor was designed using Verilog HDL and was confirmed to continue normal operation after automatically recovering error.