• Magazine of the Korea Concrete Institute
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• v.8 no.6
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• pp.205-212
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• 1996

This paper presents progressive fracture analysis of concrete using boundary element method and its stabilizing technique. To determine ultimate strength and to predict nonlinear behavior of concrete during progressive crack growth, the modelling of fracture process zone is done based on Dugdale-Barenblatt model with linear tension-softening curve. We regulate displacement and traction boundary integral equation of solids including crack boundary and analyze progressive fracture of concrete beam and compact tension specimen. Also a numerical technique which considers the growth of stress-free crack of concrete during the analysis and removes snapback of postpeak behavior is proposed.

• Journal of Satellite, Information and Communications
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• v.9 no.4
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• pp.63-68
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• 2014

Electrostatic Discharge(ESD) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different partial p-well(PPW) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device shows typical SCR-like characteristics with low on-resistance, low snapback holding voltage and low thermal breakdown voltage, which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW demonstrate the stable ESD protection performance with high latch-up immunity.

• Transactions on Electrical and Electronic Materials
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• v.7 no.1
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• pp.1-6
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• 2006

Hot carrier degradation and roll off characteristics of threshold voltage ($V_{t1}$) on NMOSFETs as I/O transistor are studied as a function of Lightly Doped Drain (LDD) structures. Pocket dose and the combination of Phosphorus (P) and Arsenic (As) dose are applied to control $V_{t1}$ roll off down to the $10\%$ gate length margin. It was seen that the relationship between $V_{t1}$ roll off characteristic and substrate current depends on P dopant dose. For the first time, we found that the n-p-n transistor triggering voltage ($V_{t1}$) depends on drain current, and both $I_{t2}$ and snapback holding voltage ($V_{sp}$) depend on the substrate current by characterization with a transmission line pulse generator. Also it was found that the improved lifetime for hot carrier stress could be obtained by controlling the P dose as loosing the $V_{t1}$ roll off margin. This study suggests that the trade-off characteristic between gate length margin and channel hot carrier (CHC) lifetime in NMOSFETs should be determined by considering Electrostatic Discharge (ESD) characteristic.

• Journal of Satellite, Information and Communications
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• v.10 no.4
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• pp.6-11
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• 2015

The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different GPNS(Gate to Primary $N^+$ Diffusion Space) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device with FPW(Full P-Well) structure and non-CPS(Counter Pocket Source) implant shows typical SCR-like characteristics with low on-resistance(Ron), low snapback holding voltage(Vh) and low thermal breakdown voltage(Vtb), which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW(Partial P-Well) structure and optimal CPS implant demonstrate the improved ESD protection performance as a function of GPNS variation. GPNS was a important parameter, which is satisfied design window of ESD protection device.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.1-7
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• 2014

A bidirectional transient voltage suppression (TVS) diode consisting of specially designed $p^--n^{{+}+}-p^-$ multi-junctions was developed using low temperature (LT) epitaxy and fabrication processes. Its electrostatic discharge (ESD) performance was investigated using I-V, C-V, and various ESD tests including the human body model (HBM), machine model (MM) and IEC 61000-4-2 (IEC) analysis. The symmetrical structure with very sharp and uniform bidirectional multi-junctions yields good symmetrical I-V behavior over a wide range of operating temperature of 300 K-450 K and low capacitance as 6.9 pF at 1 MHz. In addition, a very thin and heavily doped $n^{{+}+}$ layer enabled I-V curves steep rise after breakdown without snapback phenomenon, then resulted in small dynamic resistance as $0.2{\Omega}$, and leakage current completely suppressed down to pA. Manufactured bidirectional TVS diodes were capable of withstanding ${\pm}4.0$ kV of MM and ${\pm}14$ kV of IEC, and exceeding ${\pm}8$ kV of HBM, while maintaining reliable I-V characteristics. Such an excellent ESD performance of low capacitance and dynamic resistance is attributed to the abruptness and very unique profiles designed very precisely in $p^--n^{{+}+}-p^-$ multi-junctions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.40-50
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• 2010

The studies of PMOS transistors in CMOS technologies are reviewed- focusing on the snapback and breakdown behavior of the parasitic PNP BJTs in high current regime. A new failure mechanism of PMOSFET devices under ESD conditions is also analyzed by investigating various I/O structures in a $0.13\;{\mu}m$ CMOS technology. Localized turn-on of the parasitic PNP transistor can be caused by localized charge injection from the adjacent diodes into the body of the PMOSFET, significantly degrading the ESD robustness of PMOSFETs. Based on 2-D device simulations the critical layout parameters affecting this problem are identified. Design guidelines for avoiding this new PMOSFET failure mode are also suggested.