• 대한의용생체공학회:의공학회지
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• 제31권4호
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• pp.292-301
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• 2010

To restore visual sensation of blind patients, we have proposed a fully implantable retinal prosthesis comprising an three dimensionally (3D) stacked retinal chip for transforming optical signal to electrical signal, a flexible cable with stimulus electrode array for stimulating retina cells, and coupling coils for power transmission. The 3D stacked retinal chip is consisted of several LSI chips such as photodetector, signal processing circuit, and stimulus current generator. They are vertically stacked and electrically connected using 3D integration technology. Our retinal prosthesis has a small size and lightweight with high resolution, therefore it could increase the patients` quality of life (QOL). For realizing the fully implantable retinal prosthesis, we developed a retinal prosthesis module comprising a retinal prosthesis chip and a flexible cable with stimulus electrode array for generating optimal stimulus current. In this study, we used a 2D retinal chip as a prototype retinal prosthesis chip. We fabricated the polymide-based flexible cable of $20{\mu}m$ thickness where 16 channels Pt stimulus electrode array was formed in the cable. Pt electrode has an impedance of $9.9k{\Omega}$ at 400Hz frequency. The retinal prosthesis chip was mounted on the flexible cable by an epoxy and electrically connected by Au wire. The retinal prosthesis chip was cappted by a silicone to pretect from corrosive environments in an eyeball. Then, the fabricated retinal prosthesis module was implanted into an eyeball of a rabbit. We successfully recorded electrically evoked potential (EEP) elicited from the rabbit brain by the current stimulation supplied from the implanted retinal prosthesis module. EEP amplitude was increased linearly with illumination intensity and irradiation time of incident light. The retinal prosthesis chip was well functioned after implanting into the eyeball of the rabbit.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1016-1021
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• 2003

The overall size of electronic product is becoming small according to development of technology. Accordingly it is difficult to inspect these small components by human eyes. So, an automation system for inspecting them has been used. The existing system put microprocessor or Programmable Logic Controller (PLC) use. The structure of microprocessor-based controller and PLC use basically composed of memory devices such as ROM, RAM and I/O ports. Accordingly, the system is not only becomes complicated and enlarged but also higher price. In this paper, we implement FPGA-based One-chip Programmable Timing Controller for Inspecting Small components to resolve above problems and design the high performance controller by using VHDL. With fast development, the FPGA of high capacity that can have memory and PLL have been introduced. By using the high-capacity FPGA, the peripherals of the existent controller, such as memory, I/O ports can be implemented in one FPGA. By doing this, because the complicated system can be simplified, the noise and power dissipation problems can be minimized and it can have the advantage in price. Since the proposed controller is organized to have internal register, counter, and software routines for generating timing signals, users do not have to problem the details about timing signals and need to only send some values about an inspection system through an RS232C port. By selecting theses values appropriate for a given inspection system, desired timing signals can be generated.

• Journal of Information Processing Systems
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• 제17권1호
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• pp.191-202
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• 2021

In an Internet of Things (IoT)-configured system, each device executes on-chip software. Recent IoT devices require fast execution time of complex services, such as analyzing a large amount of data, while maintaining low-power computation. As service complexity increases, the service requires high-performance computing and more space for embedded space. However, the low performance of IoT edge devices and their small memory size can hinder the complex and diverse operations of IoT services. In this paper, we propose a remote on-demand software code execution unit using the cloudification of on-chip code memory to accelerate the program execution of an IoT edge device with a low-performance processor. We propose a simulation approach to distribute remote code executed on the server side and on the edge side according to the program's computational and communicational needs. Our on-demand remote code execution unit simulation platform, which includes an instruction set simulator based on 16-bit ARM Thumb instruction set architecture, successfully emulates the architectural behavior of on-chip flash memory, enabling embedded devices to accelerate and execute software using remote execution code in the IoT environment.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권1호
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• pp.43-50
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• 2007

In a high-speed flash style or a pipelining style analog-to-digital converter (A/D converter), the DC reference fluctuation caused by external noises becomes serious, as the sampling frequency is increased. To reduce the fluctuations in conventional A/D converters, capacitors have been simply used, but the layout area was large. Instead of capacitors, a low-noise and small-size DC reference circuit based on transmission gate (TG) is proposed in this paper. In order to verify the proposed technique, we designed and manufactured a 6-bit 2GSPS CMOS A/D converter. The A/D converter is designed with a 0.18um 1-poly 6-metal n-well CMOS technology, and it consumes 145mW at 1.8V power supply. It occupies the chip area of 977um by 1040um. The measured result shows that SNDR is 36.25 dB and INL/DNL is within 0.5LSB, even though the DC reference fluctuation is serious.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2016년도 춘계학술대회
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• pp.154-156
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• 2016

본 논문에서는 기존 위상고정루프의 아날로그 루프 필터 형태와 달리 전압제어발진기의 출력 신호로 동작하는 이산 루프 필터를 사용하여 크기는 작으면서 안정하게 동작하는 위상고정루프를 제안하였다. 샘플링과 부궤환 역할을 하는 스위치와 결합된 작은 크기의 커패시터로 하나의 칩으로 집적화가 가능한 위상고정루프는 1.8V 0.18um CMOS 공정을 이용하여 설계 하였다.

• 한국정보통신학회논문지
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• 제21권2호
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• pp.339-344
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• 2017

본 논문에서는 Early-late detector, Duty-rate modulator, 그리고 LSI(Lock Status Indicator)를 사용하여 작은 크기와 빠른 위상고정 시간을 갖는 위상고정루프를 제안하였다. 제안된 위상고정루프는 작은 용량을 가진 하나의 커패시터를 사용하게 됨으로써 칩의 크기를 결정하는 루프필터의 크기가 작아지게 되어 크기를 최소화 하였다. 기존의 전하펌프와 달리 2개의 전하펌프를 사용하여 하나의 커패시터를 사용하더라도 2차 루프필터를 사용 한 것과 같은 전압파형을 만들어 줌으로써 위상을 고정시킬 수 있다. 2개의 전하펌프는 UP, DN신호 위상의 빠르기를 감지해주는 Early-late detector와 일정한 비율의 파형을 만들어주는 Duty-rate modulator에 의해 제어된다. LSI회로를 사용함으로써 빠른 위상고정시간을 얻을 수 있다. 제안된 위상고정루프는 1.8V $0.18{\mu}m$ CMOS 공정을 사용하여 설계하였고, Hspice 시뮬레이션을 통해 회로의 동작을 검증하였다.

• 한국전자파학회논문지
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• 제23권5호
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• pp.592-597
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• 2012

본 논문에서는 휴대단말기의 Wi-Fi 대역에서 동작하는 소형 칩 안테나를 설계하였다. 제안된 안테나의 소형화를 위해 칩 안테나 하단에 후면 그라운드를 갖도록 설계하였다. 제안된 안테나는 S자 모양 대칭형으로 유전율이 3.5인 LCP(Liquid Crystal Polymer) 위에 설계되었으며, 칩 안테나의 전체 크기는 $6.0mm{\times}2.5mm{\times}1.2mm$를 갖는다. 제작된 안테나는 VSWR=3 이하 기준 300 MHz(fractional bandwidth: 12.2 %, 2.3~2.6 GHz)의 임피던스 대역폭과 peak gain은 1.42 dBi의 특성을 나타냈다. 안테나 설계는 CST Microwave Studio 상용 프로그램을 사용하여 최적화한 후, 설계된 안테나를 제작하고, 네트워크 분석기와 무반향실을 이용하여 측정하였다.

• 대한임베디드공학회논문지
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• 제14권2호
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• pp.103-111
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• 2019

The IoT-driven large-scaled systems consist of connected things with on-chip executable embedded software. These light-weighted embedded things have limited hardware space, especially small size of on-chip flash memory. In addition, on-chip embedded software in flash memory is not easy to update in runtime to equip with latest services in IoT-driven applications. It is becoming important to develop light-weighted IoT devices with various software in the limited on-chip flash memory. The remote instruction execution in cloud via IoT connectivity enables to provide high performance software execution with unlimited software instruction in cloud and low-power streaming of instruction execution in IoT edge devices. In this paper, we propose a Cloud-IoT asymmetric structure for providing high performance instruction execution in cloud, still low power code executable thing in light-weighted IoT edge environment using remote instruction execution. We propose a simulated approach to determine efficient partitioning of software runtime in cloud and IoT edge. We evaluated the instruction cloudification using remote instruction by determining the execution time by the proposed structure. The cloud-connected instruction set simulator is newly introduced to emulate the behavior of the processor. Experimental results of the cloud-IoT connected software execution using remote instruction showed the feasibility of cloudification of on-chip code flash memory. The simulation environment for cloud-connected code execution successfully emulates architectural operations of on-chip flash memory in cloud so that the various software services in IoT can be accelerated and performed in low-power by cloudification of remote instruction execution. The execution time of the program is reduced by 50% and the memory space is reduced by 24% when the cloud-connected code execution is used.

• 한국정보통신학회논문지
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• 제13권7호
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• pp.1261-1266
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• 2009

본 논문에서는 이동통신용 단말기 PCB Layout 위에 내장형 칩 안테나를 직접 설계하여 DCS(1.71${\sim}$1.88GHz) 대역, PCS(1.75${\sim}$1.87GHz) 대역 및 UPCS(1.85${\sim}$1.99GHz)대역에서 공통으로 사용할 수 있는 이동통신용 트리플밴드 칩 안테나를 설계하였다. 안테나의 특성 해석을 위해서 상용 고주파 시뮬레이션인 HFSS를 이용하였다. 트리플 광대역 특성은 1.71GHz${\sim}$1.99GHz의 대역에서 동작하는 설계된 안테나의 측정된 대역폭(V.S.W.R<2.0)을 실현시켰다. 이 안테나의 크기는 19mm${\times}$4mm${\times}$1.6mm로 설계하여 소형화시켰으며, 칩 안테나의 단점인 좁은 대역폭을 크게 개선시켰다. 그리고 실험 측정 결과들은 시뮬레이션 결과들과 매우 유사함을 보여 주었다.

• Journal of Power Electronics
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• 제16권3호
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• pp.1209-1217
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• 2016

This paper presents a novel charge pump scheme that combines the advantages of Fibonacci and Dickson charge pumps to obtain 30 V voltage for display driver integrated circuit application. This design only requires four external capacitors, which is suitable for a small-package application, such as smart card displays. High-amplitude (<6.6 V) clocks are produced to enhance the gate drive of a Dickson charge pump and improve the system's current drivability by using a voltage-doubler charge pump with a pulse skip regulator. This regulation engages many middle-voltage devices, and approximately 30% of chip size is saved. Further optimization of flying capacitors tends to decrease the total chip size by 2.1%. A precise and simple model for a one-stage Fibonacci charge pump with current load is also proposed for further efficiency optimization. In a practical design, its voltage error is within 0.12% for 1 mA of current load, and it maintains a 2.83% error even for 10 mA of current load. This charge pump is fabricated through a 0.11 μm 1.5 V/6 V/32 V process, and two regulators, namely, a pulse skip one and a linear one, are operated to maintain the output of the charge pump at 30 V. The performances of the two regulators in terms of ripple, efficiency, line regulation, and load regulation are investigated.