• International Journal of Aeronautical and Space Sciences
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• v.15 no.2
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• pp.173-182
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• 2014

The structured singular value (${\mu}$) analysis based method has many advantages for the robust stability analysis of missiles with uncertain parameters. Nevertheless, the present linear fractional transformation (LFT) modeling process, which is the basis of ${\mu}$ analysis, is complex, and not suitable for automatic implementation; on the other hand, ${\mu}$ analysis requires a large amount of computation, which is a burden for large-scale application. A constructive procedure, which is computationally more efficient, and which may lead to a lower order realization than existing algorithms, is proposed for LFT modeling. To reduce the calculation burden, an analysis method is developed, based on skew ${\mu}$. On this basis, calculation of the supremum of ${\mu}$ over a fixed frequency range converts into a single skew ${\mu}$ value calculation. Two algorithms are given, to calculate the upper and lower bounds of skew ${\mu}$, respectively. The validity of the proposed method is verified through robust stability analysis of a missile with real uncertain parameters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.1A
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• pp.47-53
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• 2003

This paper describes the design of a 155 Mb/s multiplexer-demultiplexer chip. This device for a 2.5 Gb/s SDH based transmission system is to interleave the parallel data of 51 Mb/s into 155 Mb/s serial data output, and is to deinterleave a serial input bit stream of 155 Mb/s into the parallel output of 51 Mb/s The input and output of the device are TTL compatible at the low-speed end, but 100K ECL compatible at the high-speed end The device has been fabricated with a 0.7${\mu}m$ BiCMOS gate array The fabricated chip shows the typical phase margin of 180 degrees and output data skew less than 470 ps at the high-speed end. And power dissipation is evaluated under 2.0W.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.6
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• pp.1133-1138
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• 2007

DLLs(Delay Locked Loops) have widely been used in many systems in order to achieve the clock synchronization. A SMD (Synchronous Mirror Delay) structure is used both for skew reduction and for DCC (Duty Cycle Correction). In this paper, a SMD based DLL with DCC using Reduced Delay Lines is proposed in order to reduce the clock skew and correct the duty cycle. The merged structure allows the forward delay array to be shared between the DLL and the DCC, and yields a 25% saving in the number of the required delay cells. The designed chip was fabricated using a $0.25{\mu}m$ 1-poly, 4-metal CMOS process. Measurement results showed the 3% duty cycle error when the input signal ranges from 80% to 20% and the clock frequency ranges from 400MHz to 600MHz. The locking operation needs 3 clock and duty correction requires only 5 clock cycles as feature with SMD structure.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.12
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• pp.10-18
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• 1997

The parallel trabutary signals in the SDH-based transmission system have the frame phase skew due to uneven transmission delays in the data and the clock path. This phase skew must be eliminated prior to synchronously multiplexing process. A new twenty-four channel, 51.84Mb/s DFPA(Digital Frame Phase Aligner) has been designed and fabricated in 0.8.mu.m CMOS gate array. This unique device phase-aligns the skewed input signals with refernce frame synchronous signal and reference clok for subsequent synchronous multiplexing process. the performance of fabricated device is evaluated by the STM-16 transmission system and DS-3 meansurement set. The frame phase margin of +2/-3 bit periods has been demonstrated.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.20-30
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• 2001

A 1.8V $650{\;}\textrm{mm}^2$ 4Gb DRAM having $0.10{\;}\mu\textrm{m}^2$ cell size has been successfully developed using 0.11 $\mu\textrm{m}$DRAM technology. Considering manufactur-ability, we have focused on developing patterning technology using KrF lithography that makes $0.11{\;}\mu\textrm{m}$ DRAM technology possible. Furthermore, we developed novel DRAM technologies, which will have strong influence on the future DRAM integration. These are novel oxide gap-filling, W-bit line with stud contact for borderless metal contact, line-type storage node self-aligned contact (SAC), mechanically stable metal-insulator-silicon (MIS) capacitor and CVD Al process for metal inter-connections. In addition, 80 nm array transistor and sub-80 nm memory cell contact are also developed for high functional yield as well as chip performance. Many issues which large sized chip often faces are solved by novel design approaches such as skew minimizing technique, gain control pre-sensing scheme and bit line calibration scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.20 no.2
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• pp.408-413
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• 1996

A self-diagnostic, air-damped, piezoresitive, cantilever-beam microaccelerometer has been designed, fabricated and tested for applications to automotive electronic airbag systems. A skew-symmetric proof-mass has been designed for self-diagnostic capability and zero transverse sensitivity. Two kinds of multi-step anisotropic etching processes are developed for beam thickness control and fillet-rounding formation, UV-curing paste has been used for sillicon-to-glass bounding. The resonant frequency of 2.07kHz has been measured from the fabricated devices. The sensitivity of 195 $\mu{V}$/g is obtained with a nonlinearity of 4% over $\pm$50g ranges. Flat amplitude response and frequency-proportional phase response have been obserbed, It is shown that the design and fabricaiton methods developed in the present study yield a simple, practical and effective mean for improving the performance, reliability as well as the reproducibility of the accelerometers.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.221-225
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• 2000

We designed asynchronous event logic library with 0.25$\mu\textrm{m}$ CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6㎓. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about 1.1mm ${\times}$ 1.1mm.

• The Bulletin of The Korean Astronomical Society
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• v.37 no.2
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• pp.190.1-190.1
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• 2012

과학기술위성3호는 170kg의 소형위성으로 2006년 사업을 착수하였으며, 올 2012년 12월에 러시아에서 발사할 예정이다. 주탑재체는 다목적 적외선 영상시스템 (MIRIS, Multi-Purpose IR Imaging System)으로 천문연에서 개발을 담당하였으며 우주관측과 지구관측을 수행한다. 우주관측은 $0.9-2{\mu}m$ 대역을 관측에서 은하면의 근적외선 방출광을 탐사하여 우리은하 고온가스의 기원 및 성간 난류의 물리적 특성을 연구한다. 또한 황도극지방을 추가로 관측하여 적외선 우주배경복사의 기원의 연구에 활용될 것이다. 지구관측은 $3-5{\mu}m$의 파장대역으로 한반도의 재해 및 환경변화의 연구에 활용될 예정이다. 부탑재체는 소형영상분광기 (COMIS, Compact Imaging Spectrometer)로 공주대에서 개발을 하였으며 $0.4-1.05{\mu}m$ 파장대역의 지표면 분광영상의 획득이 주요 임무이다. 소형영상분광기를 위하여 다양한 관측방법 (Strip, Stereo, Slow Skew)을 시도하며, 관측된 분광영상은 수질, 작황, 황사, 근해 환경변화 등 다양한 분야에 활용될 것으로 기대한다. 우주관측임무는 확정되어 주어진 임무기간동안 정해진 일정대로 우주관측을 수행되며, 지구관측임무는 사용자의 요구에 따라 관측지역 및 관측 횟수가 추후에 결정될 것이다. 과학기술위성3호는 기술적으로 기존 과학기술위성 시리즈 보다 향상된 위성체, 탑재체 시스템으로 주어진 우주 및 지구과학 임무를 성공적으로 수행할 것으로 예상되며, 또한 우주 및 지구과학의 연구를 위해 여러 분야에서 활동하는 국내 사용자의 적극적인 참여도 기대하고 있다. 본 발표에서는 다양한 사용자의 관측요청 접수를 위한 지상관제시스템의 설명과 임무관측을 통해 획득된 관측데이터의 전달 방법에 대해 논의한다.