• Progress in Superconductivity and Cryogenics
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• v.6 no.4
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• pp.41-45
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• 2004

Rapid Single flux quantum (RSFQ) confluence buffer is widely used in complex superconductive digital circuits. In this work, we have improved the currently used confluence buffer and obtained a more soundly designed confluence buffer. In simulations, improvements in the bias margins of 11 % and the global margins of 10%, compared to the previously used confluence buffer, were achieved. Global margins are very important in estimating a process error range allowed in fabrications. We used two circuit simulation tools, WRspice and Julia, to design and optimize the confluence buffer. We used Xic to obtain a mask layout. We fabricated the improved circuits by using Nb technology. The test results at low frequency showed that the improved confluence buffer operated correctly and had a very wide main bias margin of +/-43% enhanced from +/-26% of the previously used confluence buffer.

• Progress in Superconductivity
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• v.5 no.1
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• pp.17-20
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• 2003

We have designed and measured a SFQ(Single Flux Quantum) DFFC and an Inverter(NOT) for superconducting ALU(Arithmetic Logic Unit) development. To optimize the circuit, we used Julia, XIC, and L meter for circuit simulations and circuit layouts. The Inverter was consisted of a D Flip-Flop, a data input, a clock input and a data output. If a data pulse arrives at the inverter, then the output reads ‘0’ (no output pulse is produced) at the next clock period. If there is no input data pulse, it reads out ‘1’(output pulse is produced). The DFFC was consisted of a D flip-Flop, an Inverter, a Data in, a Clock in and two outputs. If a data pulse arrives at the DFFC circuit, then the output2 reads ‘1’ at the next clock period, otherwise it reads out ‘1’ to output1. Operation of the fabricated chip was performed at the liquid helium temperature and at the frequencies of 1KHz.

• Progress in Superconductivity
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• v.7 no.1
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• pp.36-40
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• 2005

The problem of fluctuation-induced digital errors in a rapid single flux quantum (RSFQ) circuit has been a very important issue. In this work, we calculated the bit error rate of an RSFQ switch used in superconductive arithmetic logic unit (ALU). RSFQ switch should have a very low error rate in the optimal bias. Theoretical estimates of the RSFQ error rate are on the order of $10^{-50}$ per bit operation. In this experiment, we prepared two identical circuits placed in parallel. Each circuit was composed of 10 Josephson transmission lines (JTLs) connected in series with an RSFQ switch placed in the middle of the 10 JTLs. We used a splitter to feed the same input signal to both circuits. The outputs of the two circuits were compared with an RSFQ exclusive OR (XOR) to measure the bit error rate of the RSFQ switch. By using a computerized bit-error-rate test setup, we measured the bit error rate of $2.18{\times}10^{-12}$ when the bias to the RSFQ switch was 0.398 mA that was quite off from the optimum bias of 0.6 mA.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.13-15
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• 1999

A Josephson sampler circuit using high-Tc superconductor (HTS) ramp-edge junctions has been designed, fabricated, and experimentally tested. It consists of five ramp-edge junctions with a stacked groundplane and is based on single-flux-quantum (SFQ) operations. The sampler was used to measure current waveforms at picosecond and microampere resolutions. We are developing a system based on the sampler for measuring the current waveform in a room-temperature sample. And measuring current flowing through wiring in a semiconductor large-scale integrated circuit is a promising application for the HTS sampler system.

• 한국초전도학회:학술대회논문집
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• v.14
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• pp.55-55
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• 2004

• Progress in Superconductivity
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• v.3 no.2
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• pp.172-177
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• 2002

Superconductive digital to analog converters (DAC) based on Josephson effect produce the voltage steps with high precision and good stability Therefore, they can be applied to obtain a very accurate ac voltage standard. In this paper, we made a simulation study of Rapid Single Flux Quantum (RSFQ) DAC. RSFQ DAC was composed of Non-destructive Head Out (NDRO) cells, T flip-flops, D flip-flops, Splitters, and Confluence Buffers. Confluence Buffer was used in resetting the DACs. We also obtained operating margins of the important circuit parameters in simulations.

• 한국초전도학회:학술대회논문집
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• v.11
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• pp.49-49
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• 2001

• Progress in Superconductivity
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• v.1 no.2
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• pp.81-84
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• 2000

A Josephson sampler circuit using high-Tc superconductor (HTS) ramp-edge junctions has been designed, fabricated, and experimentally tested. It consists of five ramp-edge junctions with a stacked groundplane and is based on single-flux-quantum (SFQ) operations. The sampler was used to measure current waveforms at picosecond and microampere resolutions. We are developing a system based on the sampler for measuring the current waveform in a room-temperature sample. And measuring current flowing through wiring in a semiconductor large-scale integrated circuit is a promising application for the HTS sampler system.

• Current Applied Physics
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• v.18 no.11
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• pp.1275-1279
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• 2018

We investigate the change of the Fano effect by considering one Majorana zero mode to couple laterally to the single-dot Fano interferometer. It is found that the Majorana zero mode quenches the Fano effect thoroughly and causes the conductance to be independent of the dot level, the dot-lead coupling, and the increase of the Majorana-dot coupling. As a result, the linear conductance becomes only related to the interlead coupling and the magnetic-flux phase factor. These results can be helpful for the detection of Majorana zero mode.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.71-74
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• 1999

We have fabricated high-T$_c$ superconducting YBa$_2Cu_3O_{7-{\delta}}\;/SrTiO_3/\;YBa_2Cu_3O_{7-{\delta}}$ (YBCO/STO/YBCO) multilayer structure on (001) $SrTiO_3$ substrate by using pulsed laser deposition technique for applying to ground plane of single flux quantum digital circuits. In this structure, the top and bottom YBCO layers were connected through the holes in the STO insulating layer. The critical temperature of the two YBCO layers connected each other was 86 K after annealing at 500 $^{\circ}C$ in $O_2$ atm for about 60 hr. This result shows that the annealing process is very important fabricating YBCO/STO/YBCO multilayer structure An experiment to optimize the fabrication process of YSCO/ST0/YBCO multilayer structure with good quality is in progress.