• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.62-70
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• 2007

In this paper, we design a mobile camera processor to support the MIPI CSI-2 and DPHY specification. The lane management sub-layer of CIS2 handles multi-lane configuration. Thus conceptually, the transmitter and receiver have each independent buffer on multi lanes. In the proposed architecture, the independent buffers are merged into a single common buffer. The single buffer architecture can flexibly manage data on multi lanes though the number of supported lanes are mismatched in a camera processor transmitter and a host processor. For a key issue for the data synchronization problem, the synchronization start codes are added as the starting for image data. We design synchronization logic to synchronize the received clock and to generate the byte clock. We present the verification results under proposed test bench. And we show the waves of simulation and logic synthesis results of the designed processor.

• ETRI Journal
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• v.35 no.3
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• pp.386-396
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• 2013

A 10-Gbit/s wireless communication system operating at a carrier frequency of 300 GHz is presented. The modulation scheme is amplitude shift keying in incoherent mode with a high intermediate frequency (IF) of 30 GHz and a bandwidth of 20 GHz for transmitting a 10-Gbit/s baseband (BB) data signal. A single sideband transmission is implemented using a waveguide-tapered 270-GHz high-pass filter with a lower sideband rejection of around 60 dB. This paper presents an all-electronic design of a terahertz communication system, including the major modules of the BB and IF band as well as the RF modules. The wireless link shows that, aided by a clock and data recovery circuit, it can receive $2^7$-1 pseudorandom binary sequence data without error at up to 10 Gbit/s for over 1.2 m using collimating lenses, where the transmitted power is 10 ${\mu}W$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.6
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• pp.529-534
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• 2002

Recently, As the higher frequency in clock of digital system being demanded and the density of circuits gets high for purpose of making light and minimizing system, the study for solution of digital signal distortion being interested. In this paper, the distortion of square pulse caused by dispersion as it propagates along a single microstrip line and crosstalk between lines on the Multi-Transmission Lines (MTL) is investigated. The dispersion and crosstalk of pulse signals is analyzed regarding to the structure of transmission line such as relative permittivity, substrate height, strip width of the microstrip line and pulse width of signal pulse.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.144-147
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• 2000

Data security is an important issue in today's computer networks. In order to construct a safe infra in the open communication network, a cryptography is necessarily applied to several communication application fields like a high-speed networking system supporting real-time operation. A cryptography which has already realized by a software is designed by using a hardware to improve a throughput. In this paper, we design hardware architecture of IDEA by using a single iterative round method to improve a encryption throughput. In addition, we intend to develop a hardware design methodology that a specific cryptography operate with high-speed. The hardware model is described in VHDL and synthesized by the Samsung KG 80 Library in the Synopsys development software tool. With a system clock frequency 20MHz, this hardware permits a data conversion rate of more than 116 Mbit/s.

• Journal of IKEEE
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• v.11 no.4
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• pp.358-363
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• 2007

This paper presents a floating point unit(FPU) with 3 stages for a 3D graphics shader engine. It targeted to accelerate 3D graphics in portable device environments. In order to design a balanced architecture for a shader engine, we analyzed shader assembly instructions and estimated the performance of FPU with the method we propose. The proposed unit handles 4-dimensional data through separated two paths that are lead to general operation module and special function module. The proposed FPU is compiled as a form of the cascade FPU with 3 stages to efficiently handle a matrix operation with relatively low hardware overhead. Except some complex instructions that are executed using macro instructions, all instructions complete an operation in a single instruction cycle at 100MHz frequency. A special function module performs all operations in a single clock cycle using the Newton Raphson method with the look-up table.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.817-824
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• 2016

A simultaneous bidirectional transceiver over a single wire has been developed in a 65 nm CMOS technology for a command and control bus. The echo signals of the simultaneous bidirectional link are cancelled by controlling the decision level of receiver comparators without power-hungry operational amplifier (op-amp) based circuits. With the clock information embedded in the rising edges of the signals sent from the source side to the sink side, the data is recovered by an open-loop digital circuit with 20 times blind oversampling. The data rate of the simultaneous bidirectional transceiver in each direction is 75 Mbps and therefore the overall signaling bandwidth is 150 Mbps. The measured energy efficiency of the transceiver is 56.7 pJ/b and the bit-error-rate (BER) is less than $10^{-12}$ with $2^7-1$ pseudo-random binary sequence (PRBS) pattern for both signaling directions.

• Korean Journal of Geomatics
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• v.4 no.2
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• pp.47-52
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• 2004

We can process and compute the position, velocity and time by satellite signals of GPS. The signals are used to compute positioning of three dimensions and timing offset of the receiver clock when we can track the tour satellite signals at least. One of the specified aims is to use less expensive single frequency code/carrier phase GPS receivers, which are typically around half the price of dual frequency receivers. In the study, the author analyzed the accuracy and applicability of frequence linear combination using triangulation points evaluated distance limitation.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1840-1841
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• 2007

To the Boundary Scan, this architecture in Scan testing of design under the control of boundary scan is used in boundary scan design to support the internal scan chain. The internal scan chain has single scan-in port and single scan-out port that multiple scan chain cannot be used. Internal scan design has multiple scan chains, those chains must be stitched to form a scan chain as this paper. We propose an efficient Boundary Scan test structure for multiple clock testing in design.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.8
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• pp.1440-1446
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• 2008

In this paper, a novel TMR (Triple Modular Redundancy) memory structure is proposed using state feedback control of asynchronous sequential machines. The main ability of the proposed structure is to correct the fault of SEU (Single Event Upset) asynchronously without resorting to the global synchronous clock. A state-feedback controller is combined with the TMR realized as a closed-loop asynchronous machine and corrective behavior is operated whenever an unauthorized state transition is observed so as to recover the failed state of the asynchronous machine to the original one. As a case study, an asynchronous machine modelling of TMR and the detailed procedure of controller construction are presented. A simulation results using VHDL shows the validity of the proposed scheme.

• Korean Journal of Plant Resources
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• v.32 no.5
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• pp.509-518
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• 2019

This study was conducted to investigate single crossing condition of M. sacchariflrous and M. sinensis for breeding of M. ${\times}$ giganteus cultivar. Compared with natural day length condition, cultivation in short day length condition shorten days to heading to 18~27 days in both species. Pollen germination ratio of were 75.8% at 6 o'clock in M. sacchariflorus and 51.9% at 7 o'clock in M. sinensis but decreased to below 10% at 8 o'clock in both species. When cut ears immerged in 150 mL of cut-flowers conservation solution and isolated with covering of white non-woven fabric, flowering and pollen dispersal were persisted for 7 days, and the ratio of pollen germination were above 40% for 4 days. The ratio of self-fertilization of both species were below 2.5%, but open pollenation ratio were above 50%. We obtained 437 seeds with experimental single cross of 14 combinations between tetraploid M. sacchariflorus and diploid M. siensis by application of developed single crossing methods. In the single cross, numbers of seed set were different by mother plants. Thus, the newly investigated single crossing condition will be used to breed M. ${\times}$ giganteous cultivar which is sterile and has superior characteristics of biomass yield.