Journal of IKEEE (전기전자학회논문지)
- Volume 11 Issue 4
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- Pages.358-363
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- 2007
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- 1226-7244(pISSN)
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- 2288-243X(eISSN)
A design of a floating point unit with 3 stages for a 3D graphics shader engine
- Lee, Kwang-Yeob (Department of Computer Engineering, Seokyeong University)
- Published : 2007.12.31
Abstract
This paper presents a floating point unit(FPU) with 3 stages for a 3D graphics shader engine. It targeted to accelerate 3D graphics in portable device environments. In order to design a balanced architecture for a shader engine, we analyzed shader assembly instructions and estimated the performance of FPU with the method we propose. The proposed unit handles 4-dimensional data through separated two paths that are lead to general operation module and special function module. The proposed FPU is compiled as a form of the cascade FPU with 3 stages to efficiently handle a matrix operation with relatively low hardware overhead. Except some complex instructions that are executed using macro instructions, all instructions complete an operation in a single instruction cycle at 100MHz frequency. A special function module performs all operations in a single clock cycle using the Newton Raphson method with the look-up table.