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Mobile Camera Processor Design with Multi-lane Serial Interface  

Hyun, Eu-Gin (DGIST, Department of IT)
Kwon, Soon (DGIST, Department of IT)
Lee, Jong-Hun (DGIST, Department of IT)
Jung, Woo-Young (DGIST, Department of IT)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.44, no.7, 2007 , pp. 62-70 More about this Journal
Abstract
In this paper, we design a mobile camera processor to support the MIPI CSI-2 and DPHY specification. The lane management sub-layer of CIS2 handles multi-lane configuration. Thus conceptually, the transmitter and receiver have each independent buffer on multi lanes. In the proposed architecture, the independent buffers are merged into a single common buffer. The single buffer architecture can flexibly manage data on multi lanes though the number of supported lanes are mismatched in a camera processor transmitter and a host processor. For a key issue for the data synchronization problem, the synchronization start codes are added as the starting for image data. We design synchronization logic to synchronize the received clock and to generate the byte clock. We present the verification results under proposed test bench. And we show the waves of simulation and logic synthesis results of the designed processor.
Keywords
MIPI; CSI-2; D-PHY; Mobile Camera;
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1 (주)폴리소프트, '융/복합 단말기 관련 제품 및 시장의 최근 동향', 전자부품연구원 전자정보센터 보 고서, 2006,7
2 Charng L. Lee, Kuang-Ting Hsiao, and Min-Chung Chou, 'A Low Power Mobile Camera Processor Design with SubLVDS Interface', VSLI Design, Automation and Test, 2006 International Symposium, April. 2006, pp. 1-4
3 이재영, 김민식, 이경남, '핵심부품의 고집적화에 글로벌 모바일 시장구조 변화 방향', 정보통신정책 연구원 보고서, 2005,6.1997
4 www.mipi.org
5 (주)폴리소프트, '카메라 모듈 관련 국내 기술 및 제품의 최근 동향', 전자부품연구원 전자정보센터 보고서, 2006,7
6 전주성, '이동통신 단말기술 개발 동향과 발전 방향', 전자부품연구원 전자정보센터 보고서, 2005,8