• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.6
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• pp.1247-1254
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• 2020

With the advent of the smart home era, equipment that provides confidentiality or performs authentication exists in various places in real life. Accordingly security against physical attacks is required for encryption equipment and authentication equipment. In particular, fault injection attack that artificially inject a fault from the outside to recover a secret key or bypass an authentication process is one of the very threatening attack methods. Fault sources used in fault injection attacks include lasers, electromagnetic, voltage glitches, and clock glitches. Fault injection attacks are classified into single fault injection attacks and multiple fault injection attacks according to the number of faults injected. Existing multiple fault injection systems generally use a single fault source. The system configured to inject a single source of fault multiple times has disadvantages that there is a physical delay time and additional equipment is required. In this paper, we propose a multiple fault injection system using heterogeneous fault sources. In addition, to show the effectiveness of the proposed system, the results of a multiple fault injection attack against Riscure's Piñata board are shown.

• ETRI Journal
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• v.35 no.3
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• pp.480-490
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• 2013

As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a large-scale asynchronous circuit, we design a fully clockless 32-bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top-down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre-layout simulation utilizing 0.13-${\mu}m$ CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 ${\mu}W$/MHz and is comparable to that of a synchronous counterpart.

• ETRI Journal
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• v.42 no.4
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• pp.468-479
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• 2020

The proposed AI processor architecture has high throughput for accelerating the neural network and reduces the external memory bandwidth required for processing the neural network. For achieving high throughput, the proposed super thread core (STC) includes 128 × 128 nano cores operating at the clock frequency of 1.2 GHz. The function-safe architecture is proposed for a fault-tolerance system such as an electronics system for autonomous cars. The general-purpose processor (GPP) core is integrated with STC for controlling the STC and processing the AI algorithm. It has a self-recovering cache and dynamic lockstep function. The function-safe design has proved the fault performance has ASIL D of ISO26262 standard fault tolerance levels. Therefore, the entire AI processor is fabricated via the 28-nm CMOS process as a prototype chip. Its peak computing performance is 40 TFLOPS at 1.2 GHz with the supply voltage of 1.1 V. The measured energy efficiency is 1.3 TOPS/W. A GPP for control with a function-safe design can have ISO26262 ASIL-D with the single-point fault-tolerance rate of 99.64%.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1999.11b
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• pp.173-178
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• 1999

The Trellis Coded Modulation(TCM) allows the considerable achievements of coding gains compare with conventional multi-level modulation without compromising bandwidth efficiency. In this paper, we are presented a design of the parallel Viterbi decoder for 16-QAM TCM decoder with large constraint length (K=9), which can be applicable for the Digital Audio Broadcasting(DAB) receiver. As a mid-term result, a parallel Branch Metric Calculator (BMC)can compute 16 BMs within 3 clocks and a parallel 16 Add-Compare-Selects (ACS) unit can compute in a single clock. And also, two 256 Path Metric Memories (PMM) 32 Trace Back(TB) memories are specially designed with shuffle exchange switches for 16 parallel accesses. As a VHDL simulation, we can find the correctness of proposed model, which can be operated 16 S per symbol. Now, we are performing the hardware reduction for realtime operation and FPGA implementation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.8
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• pp.777-783
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• 2009

In this paper, we implemented a wireless power transmission system at 2.45 GHz. The transmission power is limited within 20 dBm according to the ISM frequency regulations. We used two zero-bias Schottky diode and optimized the RF-DC converter for working a clock at 80 cm distance using a receiver with a single antenna and an Rf-DC converter to reduce parts and cost compared to previously reported literatures.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.2
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• pp.255-265
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• 1999

Recently the necessity of MMIC is increasing because clock frequency goes up by digital data transmission of Gbps class being demanded and the density of circuits gets high for the purpose of lightening and miniaturizing system, owing to the development of ultra high speed. When massing lines in a MMIC and super high speed integrated circuit cause the crosstalk and dispersion of signal, a digital signal is distorted and EMI is occurred. To solve this problems, It is necessary to analyze the equivalent parameters of transmission lines. This paper represent the results of the equivalent parameters of transmission lines for single and hi-level structure by using moment method.

• Journal of Sensor Science and Technology
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• v.15 no.5
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• pp.334-340
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• 2006

A compact biosignal monitoring device was developed. Electrodes for electrocardiogram (ECG) and a LED and silicon detector for photoplethysmogram (PPG) were used. A lead II type was arranged for ECG measurement and reflected light was measured at the finger tip for PPG. A single chip microprocessor (model ADuC812, Analog Device) controlled a measurement protocol and processed measured signals. PPG and ECG had a sampling rate of 300 Hz with 8-bit resolution. The maximum power consumption was 100 mW. The microprocessor computed pulse transit time (PTT) between the R-wave of ECG and the peak of PPG. To increase the resolution of PTT, analog peak detectors obtained the peaks of ECG and PPG whose interval was calculated using an internal clock cycle of 921.6 kHz. The device was designed to be operated by 3-volt battery. Biosignals can be measured for $2{\sim}3$ days continuously without the external interruptions and data is stored to an on-board memory. Our system was successfully tested with human subjects.

• Fisheries and Aquatic Sciences
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• v.4 no.3
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• pp.130-137
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• 2001

In the present study, the locomotor and feeding activities of single red sea bream, Pagrus major were simultaneously investigated to examine the existence of such dual behaviour. Seven red sea bream of 13cm body length on average were placed individually in 35L tanks equipped with an infrared sensor and a newly developed demand-feeding device. Fish were exposed to a light: dark 12: 12h cycle and constant darkness (DD) to study endogenous rhythmicity. Under LD 12: 12 h, the daily pattern of behaviour differed between individual fish; some red sea bream were diurnal and others were nocturnal. Futhermore, some of them displayed an extraordinary flexibility in phasing because they were dark active but light feeding, and vice versa. Under DD, red sea bream showed free-running rhythms for locomotor activity and feeding. These results indicate that the type of phasing of locomotor activity did not necessarily decide the feeding phase; much of this is explained by the fact that red sea bream were demand-fed. Flexibility in phasing and a certain degree of independence between locomotor and feeding activities could be seen as an adaptative response of the highly adaptable circadian rhythms of fish.

• The Transactions of the Korea Information Processing Society
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• v.4 no.6
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• pp.1565-1575
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• 1997

A new encryption algorithm had been proposed as a replacement to the Data Encryption Standard (DES) in [1,2]. It called the Extended DES (EDES) has a key length of 112 bits. The plaintext data consists of 96 bits divided into 3 sub-blocks of 32 bits each. The EDES has a potentially higher resistance to differential cryptanalysis that the DES due to the asymmetric number of f functions performed on each of the 3 sub-blocks and due to the increase of S-boxes from 8 to 16. This paper propose a hardware design for the EDES and its implementation in VLSI. The VLSI chip implements data encryption and decryption in a single hardware unit. With a system clock frequency of 15Mhz the device permits a data conversion rate of about 90Mbit/sec. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols.

• The Transactions of the Korea Information Processing Society
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• v.4 no.6
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• pp.1481-1494
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• 1997

In hard real-time systems, a timing fault may yield catastrophic results. Dynamic scheduling provides the flexibility to compensate for unexpected events at runtime; however, scheduling overhead at runtime is relatively large, constraining both the accuracy of the timing and the complexity of the scheduling analysis. In contrast, static scheduling need not have any runtime overhead. Thus, it has the potential to guarantee the precise time at which each instruction implementing a control action will execute. This paper presents a new approach to the problem of analyzing high-level language code, augmented by arbitrary before and after timing constraints, to provide a valid static schedule. Our technique is based on instruction-level complier code scheduling and timing analysis, and can ensure the timing of control operations to within a single instruction clock cycle. Because the search space for a valid static schedule is very large, a novel adaptive genetic search algorithm was developed.