Architectural Design Issues in a Clockless 32-Bit Processor Using an Asynchronous HDL |
Oh, Myeong-Hoon
(Software Research Laboratory, ETRI)
Kim, Young Woo (Software Research Laboratory, ETRI) Kwak, Sanghoon (Department of Electronics Engineering, Sogang University) Shin, Chi-Hoon (Software Research Laboratory, ETRI) Kim, Sung-Nam (IT Convergence Technology Research Laboratory, ETRI) |
1 | G.N.T. Huong and S.W. Kim, "GCC2Verilog Compiler Toolset for Complete Translation of C Programming Language into Verilog HDL," ETRI J., vol. 33, no. 5, Oct. 2011, pp. 731-740. DOI |
2 | A. Martin et al., "Three Generations of Asynchronous Microprocessors," IEEE Design Test Computers, Nov. 2003, pp. 9-17. |
3 | M.-H. Oh and S. Kim, "Asynchronous 2-Phase Protocol Based on Ternary Encoding for On-Chip Interconnect," ETRI J., vol. 33, no. 5, Oct. 2011, pp. 822-825. DOI |
4 | Semiconductor Industry Association, International Technology Roadmap for Semiconductors, 2011. |
5 | Advanced Digital Chips Inc., Instruction Set Reference Manual for AE32000: a 32-bit EISC microprocessor, Nov. 2008. |
6 | H. Lee, P. Beckett, and B. Appelbe, "High-Performance Extendable Instruction Set Computing," Proc. 6th ACSAC, Jan. 2001, pp. 89-94. |
7 | S.B. Furber and P. Day, "Four-Phase Micropipeline Latch Control Circuits," IEEE Trans. Very Large Scale Integration Syst., vol. 4, no. 2, June 1996, pp. 247-253. DOI |
8 | J. Sparso and S. Furber, Principles of Asynchronous Circuit Design - A Systems Perspective, Norwell, MA: Kluwer Academic Publishers, 2001. |
9 | N.C. Paver et al., "Register Locking in An Asynchronous Microprocessor," Proc. IEEE Int. Conf. Computer Design, Oct. 1992, pp. 351-355. |
10 | M.R. Guthaus et al., "MiBench: A Free, Commercially Representative Embedded Benchmark Suite," IEEE Int. Workshop Workload Characterization, Dec. 2001, pp. 3-14. |
11 | R. Weicker, "Dhrystone: A Synthetic Systems Programming Benchmark," Commun. ACM, vol. 27, no. 10, Oct. 1984, pp. 1013-1030. DOI ScienceOn |
12 | C.H. Van Bekel et al., "Applications of Asynchronous Circuits," Proc. IEEE, vol. 87, no. 2, Feb. 1999, pp. 223-233. DOI ScienceOn |
13 | C.J. Myers, Asynchronous Circuit Design, NY: John Wiley & Sons, Inc., July 2001. |
14 | J. Kessels and R. Marston, "Designing Asynchronous Standby Circuits for a Low-Power Pager," Proc. IEEE, vol. 87, no. 2, Feb. 1999, pp. 257-267. DOI ScienceOn |
15 | B.Z. Tang et al., "A Low Power Asynchronous GPS Baseband Processor," Proc. IEEE 18th Int. Symp. Asynchronous Circuits Syst., 2012, pp. 33-40. |
16 | S. Bo et al., "Reducing Power Consumption of Floating-Point Multiplier via Asynchronous Technique," Proc. 4th Int. Conf. Comput. Inf. Sci., Aug. 2012, pp. 1360-1363. |
17 | A. Takamura et al., "TITAC-2: An Asynchronous 32-bit Microprocessor Based on Scalable-Delay-Insensitive Model," Proc. IEEE Int. Conf. Computer Design, Oct. 1997, pp. 288-294. |
18 | Handshake Solutions, TiDE Manual, 2009 |
19 | Handshake Solutions, Haste Manual, 2009 |
20 | A. Bink and R. York, "ARM996HS: The First Licensable, Clockless 32-Bit Processor Core," IEEE Micro, vol. 27, no. 2, 2007, pp. 58-68. |
21 | J. Garside et al., "AMULET3 Revealed," Proc. IEEE Int. Symp. Adv. Research Asynchronous Circuits Syst., Apr. 1999, pp. 51-59. |