• ETRI Journal
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• v.36 no.2
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• pp.214-223
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• 2014

A fully-integrated penta-band reconfigurable power amplifier (PA) is developed for handset Tx applications. The output structure of the proposed PA is composed of the fixed output matching network, power and frequency reconfigurable networks, and post-PA distribution switches. In this work, a new reconfiguration technique is proposed for a specific band requiring power and frequency reconfiguration simultaneously. The design parameters for the proposed reconfiguration are newly derived and applied to the PA. To reduce the module size, the switches of reconfigurable output networks and post-PA switches are integrated into a single IC using a $0.18{\mu}m$ silicon-on-insulator CMOS process, and a compact size of $5mm{\times}5mm$ is thus achieved. The fabricated W-CDMA PA module shows adjacent channel leakage ratios better than -39 dBc up to the rated linear power and power-added efficiencies of higher than around 38% at the maximum linear output power over all the bands. Efficiency degradation is limited to 2.5% to 3% compared to the single-band reference PA.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.08a
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• pp.130-132
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• 2003

ALD(Atomic Layer Deposition) 법으로 박막 알루미나를 형성한 후 웨이퍼 접합과 박막화 공정으로 알루미나를 매몰절연막으로 하는 SOI 구조를 제조하고 그 특성을 조사하였다. 알루미나 박막의 유전 특성과 실리콘과의 계면 특성은 C-V 측정으로, 단면 분석은 SEM(Scanning Electron Microscope) 촬영으로 조사하였다. 알루미나와 실리콘을 접합하기 위하여 1100C에서 열처리를 행한 후 알루미나와 실리콘의 계면 상태 밀도는 $2.5{\times}10^{11}/cm^2-eV$였다. 그리고 SEM의 단연 분석과 AES(Auger Electron Spectroscope)의 깊이 방향 분석을 통해서 매몰 알루미나층의 존재를 확인하였다. 알루미나는 실리콘 산화막보다 높은 열전도성을 가지므로 이를 매몰절연막으로 하여 SOI 구조를 제조하면 기존의 실리콘산화막을 매몰절연막으로 하는 SOI를 기판으로 하여 제조되는 소자보다 selg heating 효과가 감소된 우수한 특성의 소자를 제조할 수 있다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.10
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• pp.1910-1915
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• 2007

An accurate and simple method to extract equivalent circuit parameters of fully-depleted silicon-on-insulator MOSFETs small-signal modeling operating at RF frequencies including the non-quasi static effects is presented in this article. The advantage of this method is that a unique and physically meaningful set of intrinsic equivalent circuit parameters is extracted by de-embedding procedure of extrinsic elements such as parasitic capacitances and resistances of MOSFETs from measured S-parameters using simple Z- and Y- matrices calculations. The calculated small-signal parameters using the presented extraction method give modeled Y-parameters which are in good agreement with the measured Y-parameters from 0.5 to 20GHz.

• Journal of the Korean Ceramic Society
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• v.36 no.8
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• pp.863-870
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• 1999

SOI(silicon on insulafor) was fabricated through the direct bonding using (100) Si wafer and 4$^{\circ}$off (100) Si wafer to investigate the stacking faults in silicon at the Si/SiO2 oxidized and bonded interface. The treatment time of wafer surface using MSC-1 solution was varied in order to observe the effect of cleaning on bonding characteristics. As the MSC-1 treating time increased surface hydrophilicity was saturated and surface microroughness increased. A comparison of surface hydrophilicity and microroughness with MSC-1 treating time indicates that optimum surface modified condition for time was immersed in MSC-1 for 2 min. The SOI structure directly bonded using (100) Si wafer and 4$^{\circ}$off (100) Si wafer at the room temperature were annealed at 110$0^{\circ}C$ for 30 min. Then the stacking faults at the bonding and oxidation interface were examined after the debonding. The results show that there were anomalies in the gettering of the stacking faults at the bonded region.

• Journal of the Korean institute of surface engineering
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• v.29 no.5
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• pp.482-486
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• 1996

The progress of microelectronics technology has been requiring agressive developments of device technologies. Also the requirements of the next generation devices is heading to the limits of their functions and materials, and hence asking the very specific silicon wafer such as SOI(Silicon On Insulator) wafer. The talk covers the dome stic and world-wide status of SOI device developments and applications. The presentation will also touch some predictions such as SOI device prgress schedules, impacts on the normal wafer developments, market sizes, SOI wafer prices, and so on. Finally it will cover technical aspects which are silicon oxide conditions for bonding, point defects and, surface contaminations. These points will be hopefully overcome by involved people in microelectronics industry.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.259-259
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• 2009

Surface contamination and leakage current have caused operating problems. A flashover in a substation may result in destruction of an insulator or many others electrical equipment. Engineering plastics have good characteristic (light weight, good productivity and little of void) as compare with epoxy or porcelain insulators. Outdoor insulator must have resistance to contamination. However, they are not suited to outdoor insulator by reason of being not good hydrophobic. RTV has a good property of hydrophobic and ATH has characteristic obstructing exothermic reaction. In order to reduce the incidence of insulator flashover and damage, the silicon rubber contained nano size ATH coat on surface of engineering plastics. In this paper, it compares resistance tracking of the engineering plastic coated RTV with that of non-coated engineering plastic and ATH filled composites performed much better than non-filled composites.

• Journal of the Optical Society of Korea
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• v.20 no.2
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• pp.291-299
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• 2016

We have investigated the ultimate limits of nonuniform grating couplers (NGCs) for optimized fiber coupling to silicon waveguides, compared to uniform grating couplers (UGCs). Simple grating coupler schemes, which can be fabricated in etching steps of the conventional complementary metal-oxide semiconductor (CMOS) process on silicon-on-insulator (SOI) wafers without forming any additional overlay structure, have been simulated numerically and demonstrated experimentally. Optimum values of the grating period, fill factor, and groove number for ultimate coupling efficiency of the NGCs are determined from finite-difference time-domain (FDTD) simulation, and confirmed with experimentally demonstrated devices by comparison to those for the UGCs. Our simulated results indicate that maximum coupling efficiency of NGCs is possible when the minimum pattern size is below 50 nm, but the experimental value for the maximum coupling efficiency is limited by the attainable fabrication tolerance in a practical device process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.5
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• pp.399-402
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• 2007

The effects of heat treatment on the electrical properties of strained-Si/SiGe-on-insulator (SGOI) devices were examined. We proposed the optimized heat treatment processes for improving the back interfacial electrical properties in SGOI-MOSFET. By applying the additional pre-RTA (rapid thermal annealing) before gate oxidation step and the post-RTA after source/drain dopant activation step, the electrical properties of strained-Si channel on $Si_{1-x}Ge_x$ layer were greatly improved, which resulting the improvement of the driving current, transconductance, and leakage current of SGOI-MOSFET.

• ETRI Journal
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• v.25 no.6
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• pp.503-509
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• 2003

Selective epitaxial growth (SEG) of silicon has attracted considerable attention for its good electrical properties and advantages in building microstructures in high-density devices. However, SEG problems, such as an unclear process window, selectivity loss, and nonuniformity have often made application difficult. In our study, we derived processing diagrams for SEG from thermodynamics on gas-phase reactions so that we could predict the SEG process zone for low pressure chemical vapor deposition. In addition, with the help of both the concept of the effective supersaturation ratio and three kinds of E-beam patterns, we evaluated and controlled selectivity loss and non-uniformity in SEG, which is affected by the loading effect. To optimize the SEG process, we propose two practical methods: One deals with cleaning the wafer, and the other involves inserting dummy active patterns into the wide insulator to prevent the silicon from nucleating.

• Journal of Sensor Science and Technology
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• v.19 no.2
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• pp.137-141
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• 2010

In this paper, we fabricated silicon piezoresistive pressure sensor with dry etching technology which used Deep-RIE and etching delay technology which used SOI(silicon-on-insulator) wafer. We improved pressure sensor offset and its temperature dependence by removing oxidation layer of SOI wafer which was used for dry etching delay layer. Sensitivity of the fabricated pressure sensor was about 0.56 mV/V${\cdot}$kPa at 10 kPa full-scale, and nonlinearity of the fabricated pressure sensor was less than 2 %F.S. The zero off-set change rate was less than 0.6 %F.S.