• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.20 no.4
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• pp.395-400
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• 2011

Scanning Probe Lithography is a method to localized oxidation on single crystal silicon wafer surface. This study demonstrates nanometer scale non contact lithography process on (100) silicon (p-type) wafer surface using AFM(Atomic force microscope) apparatuses and pulse controlling methods. AFM-based experimental apparatuses are connected the DC pulse generator that supplies ultra short pulses between conductive tip and single crystal silicon wafer surface maintaining constant humidity during processes. Then ultra short pulse durations are controlled according to various experimental conditions. Non contact lithography of using ultra short pulse induces electrochemical reaction between micro-scale tip and silicon wafer surface. Various growths of oxides can be created by ultra short pulse non contact lithography modification according to various pulse durations and applied constant humidity environment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.255-257
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• 2001

In this paper, the silicon rubber insulator for transmission line was experimented for 1,000 hours aging test in salt-fog condition. To evaluate and examine the aging properties of silicon rubber insulator for test, the leakage current of surface was measured. Also hydrophobicity and scanning electron microscopy were compared with initial and aged sample respectively. Above results, we can confirm that the surface properties of silicon rubber insulator easily aged by salt-fog condition.

• Journal of the Korean institute of surface engineering
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• v.28 no.3
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• pp.174-181
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• 1995

Multilayered silicon cantilever beams as interconnection systems for bare chip burn-in socket applications have been designed, fabricated and characterized. Fabrication processes of the beam are employing standard semiconductor processes such as thin film processes and epitaxial layer growth and silicon wet etching techniques. We investigated silicon etch rate in 1-3-10 etchant as functions of doping concentration, surface mechanical stress and crystal defects. The experimental results indicate that silicon etch rate in 1-3-10 etchant is strong functions of doping concentration and crystal defect density rather than surface mechanical stress. We suggested the new fabrication processes of multilayered silicon cantilever beams.

• The Journal of Natural Sciences
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• v.12 no.1
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• pp.31-39
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• 2002

Second harmonic generation was measured in porous silicon superlattices surface which were made by changing and anodization current density and the anodization time periodically in the process of obtaining porous silicon. The technique of second harmonic generation is used as a probe to the surface of porous silicon superlattice by using Nd:YAG laser. We have investigated the surface structure and nonlinear-optics properties of porous silicon superlattice.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.470-480
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• 2016

The reversal of a silicon chip to find out its security structure is common and possible at the present time. Thanks to reversing, it is possible to use a probing attack to obtain useful information such as personal information or a cryptographic key. For this reason, security-related blocks such as DES (Data Encryption Standard), AES (Advanced Encryption Standard), and RSA (Rivest Shamir Adleman) engines should be located in the lower layer of the chip to guard against a probing attack; in this regard, the addition of a silicon-surface-protection layer onto the chip surface is a crucial protective measure. But, for manufacturers, the implementation of an additional silicon layer is burdensome, because the addition of just one layer to a chip significantly increases the overall production cost; furthermore, the chip size is increased due to the bulk of the secure logic part and routing area of the silicon protection layer. To resolve this issue, this paper proposes a practical silicon-surface-protection method using a metal layer that increases the security level of the chip while minimizing its size and cost. The proposed method uses a shift register for the alternation and variation of the metal-layer data, and the inter-connection area is removed to minimize the size and cost of the chip in a more extensive manner than related methods.

• Journal of the Korean Society for Heat Treatment
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• v.26 no.4
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• pp.178-184
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• 2013

The effects of thickness and surface grinding condition on the fracture strength of Si wafer with a thickness under $100{\mu}m$ were investigated. Fracture strength was measured by ball breaker test for about 330 dies (size: $4mm{\times}4mm$) per each wafer. For statistical analysis of the fracture strength, scale factor was determined from Weibull plot. Ball breaker fracture strength was observed to increase with decreasing thickness of silicon die. For the silicon dies of different surface conditions, ball breaker fracture strength was high in the order of polished, ground (#4800), and ground (#320 grit) specimen. Probabilistic fracture strength (i.e., scale factor) increased with decreasing surface roughness of silicon die.

• 한국신재생에너지학회:학술대회논문집
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• 2007.06a
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• pp.295-298
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• 2007

Reduction of optical losses in crystalline silicon solar cells by surface modification is one of the most important issues of silicon photovoltaics. Porous Si layers on the front surface of textured Si substrates have been investigated with the aim of improving the optical losses of the solar cells, because an anti-reflection coating(ARC) and a surface passivation can be obtained simultaneously in one process. We have demonstrated the feasibility of a very efficient porous Si ARC layer, prepared by a simple, cost effective, electrochemical etching method. Silicon p-type CZ (100) oriented wafers were textured by anisotropic etching in sodium carbonate solution. Then, the porous Si layers were formed by electrochemical etching in HF solutions. After that, the properties of porous Si in terms of morphology, structure and reflectance are summarized. The structure of porous Si layers was investigated with SEM. The formation of a nanoporous Si layer about 100nm thick on the textured silicon wafer result in a reflectance lower than 5% in the wavelength region from 500 to 900nm. Such a surface modification allows improving the Si solar cell characteristics. An efficiency of 13.4% is achieved on a monocrystalline silicon solar cell using the electrochemical technique.

• Korean Journal of Materials Research
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• v.19 no.1
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• pp.18-23
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• 2009

The influence of various surface morphologies on the mechanical strength of silicon substrates was investigated in this study. The yield for the solar cell industry is mainly related to the fracturing of silicon wafers during the manufacturing process. The flexural strengths of silicon substrates were influenced by the density of the pyramids as well as by the size and the rounded surface of the pyramids. To characterize and optimize the relevant texturing process in terms of mechanical stability and the fabrication yield, the mechanical properties of textured silicon substrates were investigated to optimize the size and morphology of random pyramids. Several types of silicon substrates were studied, including the planar type, a textured surface with large and small pyramids, and a textured surface with rounded pyramids. The surface morphology and a cross-section of the as-textured and fractured silicon substrates were investigated by scanning electron microscopy.

• Journal of Integrative Natural Science
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• v.5 no.4
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• pp.211-215
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• 2012

Single-crystalline silicon nanowire arrays (SiNWAs) using electroless metal-assisted etchings of p-type silicon were successfully fabricated. Ag nanoparticle deposition on silicon wafers in HF solution acted as a localized micro-electrochemical redox reaction process in which both anodic and cathodic process took place simultaneously at the silicon surface to give SiNWAs. The growth effect of SiNWs was investigated by changing of etching times. The morphologies of SiNWAs were obtained by SEM observation. Well-aligned nanowire arrays perpendicular to the surface of the silicon substrate were produced. Optical characteristics of SiNWs were measured by FT-IR spectroscopy and indicated that the surface of SiNWs are terminated with hydrogen. The thicknesses and lengths of SiNWs are typically 150-250 nm and 2 to 5 microns, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.602-606
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• 2003

Silicon has been developed as an alternate anode material for lithium secondary batteries. A simple approach to improve the electrical contact of silicon powder has described. Carbon-coated and silver-coated silicon have been prepared by chemical vapor deposition and electroless plating respectively. Assembled cells, which consisted of surface modified silicon, lithium foil and $Li^+$ contained organic electrolyte, have been studied using electrochemical methods. Carbon-coated silicon was improved in the electrochemical performance such as reversibility and resistance compared to surface-unmodified silicon.