• Journal of the Korean institute of surface engineering
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• v.27 no.2
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• pp.83-90
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• 1994

We have investigated the mechanism for the abnormal oxide growth occuring during oxidation of the crystalline tungsten silicide. TEM and XPS analysis reveal the abnormaly grown oxide layer consisting of crystalline $Wo_3$ and amorphous $SiO_2$. The presence of crystalline $Wo_3$ provides a rapid diffusion of oxygen through the oxide layer. The abnormal oxide growth is mainly due to the poor quality of initial oxide layer growth on tungsten silicide. Two species such as tungsten and silicon from decomposition fo tungsten silicide as well as silicon supplied from the underlying polysilicon are the main contributors sto abnormal oxide forma-tion. Consequently, the abnormal oxidation results in the disintegration of tungsten silicide and thinning of polysilicon as well.

• Transactions on Electrical and Electronic Materials
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• v.12 no.1
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• pp.16-19
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• 2011

The oxide-nitride-oxide (ONO) deposition process was added to the beginning of a 0.25 ${\mu}m$ embedded polysiliconoxide-nitride-oxide-silicon (SONOS) process before all of the logic well implantation processes in order to maintain the characteristics of basic CMOS(complementary metal-oxide semiconductor) logic technology. The system subsequently suffered severe ONO rupture failure. The damage was caused by the ONO implantation and was responsible for the ONO rupture failure in the embedded SONOS process. Furthermore, based on the experimental results as well as an implanted ion's energy loss model, processes primarily producing permanent displacement damages responsible for the ONO rupture failure were investigated for the embedded SONOS process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.34 no.2
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• pp.142-147
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• 2021

We present a subthreshold swing model for a symmetric junctionless double gate MOSFET. The scale length λ1 required to obtain the potential distribution using the Poisson's equation is a criterion for analyzing the short channel effect by an analytical model. In general, if the channel length Lg satisfies Lg > 1.5λ1, it is known that the analytical model can be sufficiently used to analyze short channel effects. The scale length varies depending on the channel and oxide thickness as well as the dielectric constant of the channel and the oxide film. In this paper, we obtain the scale length for a constant permittivity (silicon and silicon dioxide), and derive the relationship between the scale length and the channel length satisfying the error range within 5%, compared with a numerical method. As a result, when the thickness of the oxide film is reduced to 1 nm, even in the case of Lg < λ1, the analytical subthreshold swing model proposed in this paper is observed to satisfy the error range of 5%. However, if the oxide thickness is increased to 3 nm and the channel thickness decreased to 6 nm, the analytical model can be used only for the channel length of Lg > 1.8λ1.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1442-1444
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• 1995

In this study, we confirmed that the crystallinity and the mechanical properties of polycrystalline Silicon(poly-Si) deposited on the poly-oxide are better than those of poly-Si on the conventional sacrificial layers that is CVD oxide layer or PSG. But the etch rate of poly-oxide is poor than that of the CVD oxide layer or PSG. Therefore, to make the best use of small stress and fast etch rate, we fabricated the double oxide layer; 10%-thick poly-oxide on 90%-thick CVD oxide or PSG. To estimate structure deformation by stress, we fabricated the test structures; cantilever. bridge and ring/beam structure and estimated by SEM. As the results, all structure is expressed the deformed structure by residual stress(tensile stress) and the deformation of the structure layer on the double oxide layer is small compared with that of the structure layer on the CVD oxide layer or PSG. And, the etch rate of the double oxide layer is enhanced compared with that of the poly-oxide.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1327-1329
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• 1998

It is very important to select superior inter-layer PMD(Pre Metal Dielectric) materials which can act as penetration barrier to various impurities created by CMP processes. In this paper, hot carrier degradation and device characteristics were studied with material variation of PMD-1 layers, which were split by LP-TEOS, SR-Oxide, PE-Oxynitride, PE-Nitride, PE-TEOS films. It was observed that the oxynitride and nitride using plasma was greatly decreased in hot carrier effect in comparison with silicon oxide. Consequently, silicon oxide turned out to be a better PMD-1 material than PE-oxynitride and PE-nitride. Also, LP-TEOS film was the best PMD-1 material Among the silicon oxides.

• The Korean Journal of Ceramics
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• v.4 no.3
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• pp.222-226
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• 1998

$Cu_3N$ film deposited on silicon oxide substrate by r.f. reactive sputtering technique. Synthesis and properties of copper nitride film were investigated for its possible application to Cu metallization as adhesive interlayer between copper and $SiO_2. Cu_3N$ film was synthesized at the substrate temperature ranging from $100^{\circ}C$ to $200^{\circ}C$ and at nitrogen gas ratio above $X_{N2}=0.4. Cu_3N, CuN_x$, and FGM-structured $Cu/CuN_x$ films prepared in this work passed Scotch-tape test and showed improved adhesion property to silicon oxide substrate compared with Cu film. Electrical resistivity of copper nitride film had a dependency on its lattice constant and was ranged from 10-7 to 10-1 $\Omega$cm. Copper nitride film was, however, unstable when it was annealed at the temperature above $400^{\circ}C$.

• Progress in Superconductivity and Cryogenics
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• v.20 no.4
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• pp.20-25
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• 2018

Niobium nitride (NbN) superconducting thin films with the thickness of 100 and 400 nm have been deposited on the surfaces of silicon oxide/silicon substrates using a sputtering method. Their superconducting properties have been evaluated in terms of the transition temperature, critical magnetic field, and critical current density. In addition, the NbN films were patterned in a line with a width of $10{\mu}m$ by a reactive ion etching (RIE) process for their characterization. This study proves the applicability of the standard complementary metal-oxide-semiconductor (CMOS) process in the fabrication of superconducting thin films without considerable degradation of superconducting properties.

• Journal of information and communication convergence engineering
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• v.4 no.2
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• pp.84-87
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• 2006

Lateral distributions of locally injected electrons and holes in an oxide-nitride-oxide (ONO) dielectric stack of two different silicon-oxide-nitride-oxide-silicon (SONOS) memory cells are evaluated by single-junction charge pumping technique. Spatial distribution of electrons injected by channel hot electron (CHE) for programming is limited to length of the ONO region in a locally ONO stacked cell, while is spread widely along with channel in a fully ONO stacked cell. Hot-holes generated by band-to-band tunneling for erasing are trapped into the oxide as well as the ONO stack in the locally ONO stacked cell.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.364-365
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• 2005

This paper report nanotribological behavior between Si tip and Cu wafer surfaces which was treated various concentration of $H_2O_2$. This experimental approach has proven atomic level insight into Cu CMP. It has been used to study interfacial friction and adhesion force between Si tip and Cu wafer surfaces in air by atomic force microscopy (AFM). Adhesion force of Cu surfaces which was pre-cleaned in diluted HF solution was lager than Cu oxide surfaces. Adhesion force of Cu oxide surface was saturated around 7 nN. Slope of normal force vs lateral signal was increased as increasing concentration of $H_2O_2$ and it was saturated around 24. Friction force of Cu oxide was lager than Cu.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.10
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• pp.451-457
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• 2003

The silicon wafer is stable status at room temperature, but it is weak at high temperatures which is necessary for it to be fabricated into a power semiconductor device. During thermal diffusion processing, a high temperature produces a variety thermal stress to the wafer, resulting in device failure mode which can cause unwanted oxide charge or some defect. This disrupts the silicon crystal structure and permanently degrades the electrical and physical characteristics of the wafer. In this paper, the electrical characteristics of a single oxide layer due to high temperature diffusion process, wafer resistivity and thickness of polyback was researched. The oxide quality was examined through capacitance-voltage characteristics, defect density and BMD(Bulk Micro Defect) density. It will describe the capacitance-voltage characteristics of the single oxide layer by semiconductor process and device simulation.