• 제목/요약/키워드: silicon cap

검색결과 23건 처리시간 0.031초

스트레인드 채널이 무캐패시터 메모리 셀의 메모리 마진에 미치는 영향 (Impact of strained channel on the memory margin of Cap-less memory cell)

  • 이충현;김성제;김태현;오정미;최기령;심태헌;박재근
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2009년도 하계학술대회 논문집
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    • pp.153-153
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    • 2009
  • We investigated the dependence of the memory margin of the Cap-less memory cell on the strain of top silicon channel layer and also compared kink effect of strained Cap-less memory cell with the conventional Cap-less memory cell. For comparison of the characteristic of the memory margin of Cap-less memory cell on the strain channel layer, Cap-less transistors were fabricated on fully depleted strained silicon-on-insulator of 0.73-% tensile strain and conventional silicon-on-insulator substrate. The thickness of channel layer was fabricated as 40 nm to obtain optimal memory margin. We obtained the enhancement of 2.12 times in the memory margin of Cap-less memory cell on strained-silicon-on-insulator substrate, compared with a conventional SOI substrate. In particular, much higher D1 current of Cap-less memory cell was observed, resulted from a higher drain conductance of 2.65 times at the kink region, induced by the 1.7 times higher electron mobility in the strain channel than the conventional Cap-less memory cell at the effective field of 0.3MV/cm. Enhancement of memory margin supports the strained Cap-less memory cell can be promising substrate structures to improve the characteristics of Cap-less memory cell.

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비정형 콘크리트 패널의 정확성 향상을 위한 하부 다점 프레스의 거푸집 연결기술에 관한 연구 (A Study on the Mold Connecting Technology of the Lower Multi-point Press for Improving Accuracy of Free-form Concrete Panels)

  • 윤지영;윤종영;이동훈
    • 한국건축시공학회:학술대회논문집
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    • 한국건축시공학회 2021년도 가을 학술논문 발표대회
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    • pp.6-7
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    • 2021
  • Although the development of free-form architectural technology continues, it consumes a lot of money and time due to the one-time formwork and the difficulty of maintaining quality due to manual work. To this end, in this study, a shape connection technique was proposed and verified to improve the limitations of implementing the curved surface of the existing lower multi-point press. In order to improve the accuracy of the shape, a curved surface was implemented using a silicon cap and a silicon plate. As a result of the error analysis of the shape, a small value of less than 3 mm was found. This study can implement more accurate curved surfaces than conventional technologies and produce high-quality free-form panels.

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자동 닫힘 기능을 갖는 마찰힌지 개발에 관한 연구 (A Study on the Development of Friction Hinge with Automatic Closed Function)

  • 예상돈;민병현
    • 한국기계가공학회지
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    • 제13권1호
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    • pp.107-114
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    • 2014
  • A friction hinge system which moves without power was designed and developed using the principle of friction force, which is caused by interference between the inner diameter of a silicon cap and the outer diameter of a cylindrical roller bearing with one-way rotation in a counterclockwise direction. The system was applied to the lid of buffet ware, which moved up by external force and moved down by gravitational force. However, design conditions which included a rotation angle of the hinge of more than 80 degrees and a closing time of more than 20 seconds were required when the lid of the buffet ware closed due to gravitational force. The design safety of the friction hinge body connected to the lid of the buffet ware from the hinge system was checked on the basis of structural, fatigue and thermal analyses. The material of the shaft, cap and flange among the hinge elements was changed to polyethylene from steel to reduce the weight of the friction hinge system. An injection molding simulation was performed and injection molds of the shaft, cap and flange were created. The weight of the hinge system was decreased from 805g to 219g.

고온 열처리 공정이 탄화규소 쇼트키 다이오드 특성에 미치는 영향 (Effect of High Temperature Annealing on the Characteristics of SiC Schottky Diodes)

  • 정희종;방욱;강인호;김상철;한현숙;김형우;김남균;이용재
    • 한국전기전자재료학회논문지
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    • 제19권9호
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    • pp.818-824
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    • 2006
  • The effects of high-temperature process required to fabricate the SiC devices on the surface morphology and the electrical characteristics were investigated for 4H-SiC Schottky diodes. The 4H-SiC diodes without a graphite cap layer as a protection layer showed catastrophic increase in an excess current at a forward bias and a leakage current at a reverse bias after high-temperature annealing process. Moreover it seemed to deviate from the conventional Schottky characteristics and to operate as an ohmic contact at the low bias regime. However, the 4H-SiC diodes with the graphite cap still exhibited their good electrical characteristics in spite of a slight increase in the leakage current. Therefore, we found that the graphite cap layer serves well as the protection layer of silicon carbide surface during high-temperature annealing. Based on a closer analysis on electric characteristics, a conductive surface transfiguration layer was suspected to form on the surface of diodes without the graphite cap layer during high-temperature annealing. After removing the surface transfiguration layer using ICP-RIE, Schottky diode without the graphite cap layer and having poor electrical characteristics showed a dramatic improvement in its characteristics including the ideality factor[${\eta}$] of 1.23, the schottky barrier height[${\Phi}$] of 1.39 eV, and the leakage current of $7.75\{times}10^{-8}\;A/cm^{2}$ at the reverse bias of -10 V.

비선형 접촉문제 해석을 통한 얼음 디스펜서 덕트 캡 조립체의 밀봉성능 평가 및 개선방안 연구 (A Study on Evaluation and Improvement of Sealing Performance of Duct Cap Assembly for Ice Dispenser By Nonlinear Contact Problem Analysis)

  • 이부윤
    • 한국기계가공학회지
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    • 제17권2호
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    • pp.37-46
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    • 2018
  • Present research is to evaluate and improve the sealing performance of the duct cap assembly for the ice dispensers through structural analysis. The nonlinear contact problems to check the sealing performance were analyzed using ANSYS software. The results of the analyses related to the sealing performance: the displacement distribution, the contact condition between the cap-silicon and the case, and the pressure distribution on the contact surface, were examined and discussed. Based on the results of the existing design of the duct cap assembly, two cases of the design modifications to improve the sealing performance were introduced. By examining the results of the two cases, a final design improvement plan was proposed and analyzed. It is shown that the sealing performance of the proposed final design is much more favorable than the existing design. The method of structural analysis and design improvement of the duct cap assembly presented in this paper will help improve the sealing performance of the ice dispenser duct caps.

Cahn Balance를 이용한 급속 가열방식의 석탄가스화 장치 소개 (An Introduction of an Apparatus for Rapid Heating Coal Gasification)

  • 이중기;이성호;임태훈
    • 공업화학
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    • 제2권4호
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    • pp.393-398
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    • 1991
  • 실제 실험 시간에 따른 시료의 무게변화와 생성가스의 조성 측정을 동시에 진행할 수 있는 실험실 규모의 장치를 칸 발란스를 이용하여 제작하였다. 급속 가열이 가능하도록 텅스텐 할로겐 등을 이용한 복사가열 방식을 채택하였고 시료 접시는 복사열을 충분히 흡수하도록 흑연을 사용하였다. 석탄가스화 실험조건에서 이 흑연이 반응기체와 반응하는 것을 막기위하여 실리콘나이트로 코팅하였고, 시료접시 바로 밑에 위치한 열전쌍에도 같은 방식으로 제작된 흑연 모자를 씌워 복사열 흡수능력이 서로 다른 흑연(시료접시)과 금속체(열전쌍) 사이에서 생길 수 있는 온도 측정의 오차를 최소화 하도록 하였다. 이 장치를 사용한 결과 상온에서 섭씨 800도까지 3 분 이내에 온도상승이 가능하였으며 시료 접시의 무게변화없이 실험중 석탄 시료의 무게 변화와 가스조성을 동시에 측정할 수 있었다.

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Strained-SiGe Complementary MOSFETs Adopting Different Thicknesses of Silicon Cap Layers for Low Power and High Performance Applications

  • Mheen, Bong-Ki;Song, Young-Joo;Kang, Jin-Young;Hong, Song-Cheol
    • ETRI Journal
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    • 제27권4호
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    • pp.439-445
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    • 2005
  • We introduce a strained-SiGe technology adopting different thicknesses of Si cap layers towards low power and high performance CMOS applications. By simply adopting 3 and 7 nm thick Si-cap layers in n-channel and p-channel MOSFETs, respectively, the transconductances and driving currents of both devices were enhanced by 7 to 37% and 6 to 72%. These improvements seemed responsible for the formation of a lightly doped retrograde high-electron-mobility Si surface channel in nMOSFETs and a compressively strained high-hole-mobility $Si_{0.8}Ge_{0.2}$ buried channel in pMOSFETs. In addition, the nMOSFET exhibited greatly reduced subthreshold swing values (that is, reduced standby power consumption), and the pMOSFET revealed greatly suppressed 1/f noise and gate-leakage levels. Unlike the conventional strained-Si CMOS employing a relatively thick (typically > 2 ${\mu}m$) $Si_xGe_{1-x}$ relaxed buffer layer, the strained-SiGe CMOS with a very thin (20 nm) $Si_{0.8}Ge_{0.2}$ layer in this study showed a negligible self-heating problem. Consequently, the proposed strained-SiGe CMOS design structure should be a good candidate for low power and high performance digital/analog applications.

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Delayed auger recombination in silicon measured by time-resolved X-ray scattering

  • Jo, Wonhyuk;Landahl, Eric C.;Kim, Seongheun;Lee, Dong Ryeol;Lee, Sooheyong
    • Current Applied Physics
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    • 제18권11호
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    • pp.1230-1234
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    • 2018
  • We report a new method of measuring the non-radiative recombination rate in bulk Silicon. Synchrotron timeresolved x-ray scattering (TRXS) combines femtometer spatial sensitivity with nanosecond time resolution to record the temporal evolution of a crystal lattice following intense ultrafast laser excitation. Modeling this data requires an Auger recombination time that is considerably slower than previous measurements, which were made at lower laser intensities while probing only a relatively shallow surface depth. We attribute this difference to an enhanced Coulomb interaction that has been predicted to occur in bulk materials with high densities of photoexcited charge carriers.

Implant Anneal Process for Activating Ion Implanted Regions in SiC Epitaxial Layers

  • Saddow, S.E.;Kumer, V.;Isaacs-Smith, T.;Williams, J.;Hsieh, A.J.;Graves, M.;Wolan, J.T.
    • Transactions on Electrical and Electronic Materials
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    • 제1권4호
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    • pp.1-6
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    • 2000
  • The mechanical strength of silicon carbide dose nor permit the use of diffusion as a means to achieve selective doping as required by most electronic devices. While epitaxial layers may be doped during growth, ion implantation is needed to define such regions as drain and source wells, junction isolation regions, and so on. Ion activation without an annealing cap results in serious crystal damage as these activation processes must be carried out at temperatures on the order of 1600$^{\circ}C$. Ion implanted silicon carbide that is annealed in either a vacuum or argon environment usually results in a surface morphology that is highly irregular due to the out diffusion of Si atoms. We have developed and report a successful process of using silicon overpressure, provided by silane in a CAD reactor during the anneal, to prevent the destruction of the silicon carbide surface, This process has proved to be robust and has resulted in ion activation at a annealing temperature of 1600$^{\circ}C$ without degradation of the crystal surface as determined by AFM and RBS. In addition XPS was used to look at the surface and near surface chemical states for annealing temperatures of up to 1700$^{\circ}C$. The surface and near surface regions to approximately 6 nm in depth was observed to contain no free silicon or other impurities thus indicating that the process developed results in an atomically clean SiC surface and near surface region within the detection limits of the instrument(${\pm}$1 at %).

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열화학기상증착법에 의해 실리콘 기판위에 수직방향으로 정렬된 탄소나노튜브의 성장 (Growth of vertically aligned carbon nanotubes on silicon substrates by the thermal CVD)

  • 이철진;김대운;이태재;박정훈;손권희;류승철;최영철;박영수;최원석
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1999년도 하계종합학술대회 논문집
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    • pp.275-278
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    • 1999
  • We have grown vertically aligned carbon nanotubes in a large area of Co-Ni codeposited Si substrates by the thermal CVD using $C_2$H$_2$gas. Since the discovery of carbon nanotubes, Synthesis of carbon nanotubes for mass production has been achieved by several methods such as laser vaporization, arc discharge, and pyrolysis. In particular, growth of vertically aligned nanotubes is of technological importance for applications to FED. Recently, vertically aligned carbon nanotubes have been grown on glass by PECVD. Aligned carbon nanotubes can be also grown on mesoporous silica and Fe patterned porous silicon using CVD. Despite such breakthroughs in the growth, the growth mechanism of the alignment are still far from being clearly understood. Furthermore, FED has not been clearly demonstrated yet at a practical level. Here, we demonstrate that carbon nanotubes can be vertically aligned on catalyzed Si substrate when the domain density reaches a certain value. We suggest that steric hindrance between nanotubes at an initial stage of the growth forces nanotubes to align vertically and then nanotubes are further grown by the cap growth mechanism.

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