• Composites Research
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• 제25권6호
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• pp.172-177
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• 2012

저저항 Si-SiC 소결체 제조를 위해 ${\alpha}$-SiC에서 조성과 C의 양을 변화시키면서 반응소결 특성을 고찰하였다. 시료준비는 정수압으로 성형체를 제조하였고, 용융Si 반응소결을 통해 시험편을 준비하였다. 반응소결체의 미세구조, 기계적 특성 및 전기저항 분석 결과 용융Si과 반응 후 미립의 ${\beta}$-SiC가 생성되었고, 치밀한 소결체를 형성하였다. 미립 ${\beta}$-SiC 생성량은 카본 양 에 따라 증가하였다. 그리고 C함량 10wt%이내에서 기계 R전기저항특성은 입도조성 영향이 크고 카본 함량 10wt%이상에서는 상전이 반응의 영향이 큼을 알 수 있었다.

• 대한금속재료학회지
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• 제49권4호
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• pp.321-328
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• 2011

The 30 nm-thick Ni layers was deposited on a flexible polyimide substrate with an e-beam evaporation. Subsequently, we deposited a Si layer using a catalytic CVD (Cat-CVD) in a hydride amorphous silicon (${\alpha}$-Si:H) process of $T_{s}=180^{\circ}C$ with varying thicknesses of 55, 75, 145, and 220 nm. The sheet resistance, phase, degree of the crystallization, microstructure, composition, and surface roughness were measured by a four-point probe, HRXRD, micro-Raman spectroscopy, FE-SEM, TEM, AES, and SPM. We confirmed that our newly proposed Cat-CVD process simultaneously formed both NiSi and crystallized Si without additional annealing. The NiSi showed low sheet resistance of < $13{\Omega}$□, while carbon (C) diffused from the substrate led the resistance fluctuation with silicon deposition thickness. HRXRD and micro-Raman analysis also supported the existence of NiSi and crystallized (>66%) Si layers. TEM analysis showed uniform NiSi and silicon layers, and the thickness of the NiSi increased as Si deposition time increased. Based on the AES depth profiling, we confirmed that the carbon from the polyimide substrate diffused into the NiSi and Si layers during the Cat-CVD, which caused a pile-up of C at the interface. This carbon diffusion might lessen NiSi formation and increase the resistance of the NiSi.

• Current Photovoltaic Research
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• 제8권3호
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• pp.94-101
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• 2020

This study was trying to focus on achieving high efficiency of multi junction solar cell with thin film silicon solar cells. The proposed thin film Si-Ge/c-Si tandem junction solar cell concept with a combination of low-cost thin-film silicon solar cell technology and high-efficiency c-Si cells in a monolithically stacked configuration. The tandem junction solar cells using amorphous silicon germanium (a-SiGe:H) as an absorption layer of upper sub-cell were simulated through ASA (Advanced Semiconductor Analysis) simulator for acquiring the optimum structure. Graded Ge composition - effect of E_g profiling and inserted buffer layer between absorption layer and doped layer showed the improved current density (J_sc) and conversion efficiency (η). 13.11% conversion efficiency of the tandem junction solar cell was observed, which is a result of showing the possibility of thin film Si-Ge/c-Si tandem junction solar cell.

• 대한전기학회논문지
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• 제41권2호
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• pp.170-177
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• 1992

Contact resistance and contact leakage current of the Al/TiSiS12T/Si system are investigated for NS0+T and PS0+T junctions. SALICIDE (Self Aligned Silicide) process was used to make the Al/TiSiS12T/Si system. Titanium disilicide is one of the most common silicides because of its thermal stability, ability to form selective formation and low resistivity. In this paper, RTA temperature effect and Junction implant dose effect were evaluated to characterize contact resistance and contact leakage current. The TiSiS12T contact resistance to NS0+T silicon is lower than that to PS0+T silicon, and TiSiS12T of contact leakage current to NS0+T silicon is lower than that to PS0+T silicon. Contact resistance and contact leakage current of the Al/TiSiS12T/Si system by this method were possible for VLSI application.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1065-1068
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• 2003

For the first time, high quality ultra-thin strained Si/SiGe on Insulator (SGOI) substrate with total SGOI thickness( $T_{Si}$ + $T_{SiGe}$) of 13 nm is developed to combine the device benefits of strained silicon and SOI. In the case of 6- 10 nm-thick top silicon, 100-110 % $I_{d,sat}$ and electron mobility increase are shown in long channel nFET devices. However, 20-30% reduction of $I_{d,sat}$ and electron mobility are observed with 3 nm top silicon for the same long channel device. These results clearly show that the FETs operates with higher performance due to the strain enhancement from the insertion of SiGe layer between the top silicon layer and the buried oxide(BOX) layer. The performance degradation of the extremely thin( 3 nm ) top Si device can be attributed to the scattering of the majority carriers at the interfaces.

• 한국전기전자재료학회논문지
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• 제13권2호
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• pp.95-100
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• 2000

For the well-controlled growing in-situ heavily phosphorus doped polycrystalline Si films directly on Si wafer by reduced pressure chemical vapor deposition, a study is made of the two step growth. When in-situ heavily phosphorus doped Si films were deposited directly on Si (100) wafer, crystal structure in the film is not unique, that is, the single crystal to polycrystalline phase transition occurs at a certain thickness. However, the well-controlled polycrtstalline Si films deposited by two step growth grew directly on Si wafers. Moreover, the two step growth, which employs crystallization of grew directly on Si wafers. Moreover, the two step growth which employs crystallization of amorphous silicon layer grown at low temperature, reveals crucial advantages in manipulating polycrystal structures of in-situ phosphorous doped silicon.

• 한국세라믹학회지
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• 제42권5호
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• pp.359-365
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• 2005

Silicon nitride coating films with various ratios of nitrogen to silicon contents were prepared and characterized. The film was coated on silicon substrate by sputtering method with changing nitrogen gas flow rate in a chamber. The nitrogen to silicon ratio was found to have values in a range from 0 to 1.4. Coated film was characterized with scanning electron microscopy, transmission electron microscopy, electron probe microanalysis, nanoindentation scanning probe microscopy, x-ray photon spectrometry, and Raman spectrometry. Silicon nitride phase in all samples showed amorphous nature regardless of N/Si ratio. When N/Si ratio was 1.25, hardness and elastic modulus of silicon nitride film showed maximum with 22 GPa and 210 GPa, respectively. Those values decreased, when N/Si ratio was higher than 1.25. Raman spectrum showed that no silicon phase exist in the film. XPS result showed that the silicon-nitrogen bond was dominant way for atomic bonding in the film. The structure and property was explained with Random Bonding Model(RBM) which was consistent with the microstructure and chemistry analysis for the coating films.

• 한국태양에너지학회:학술대회논문집
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• 한국태양에너지학회 2012년도 춘계학술발표대회 논문집
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• pp.243-247
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• 2012

The paper focuses on an anti-reflection (AR) coating deposited by PECVD in silicon solar cell fabrication. AR coating is effective to reduce the reflection of the light on the silicon wafer surface and then increase substantially the solar cell conversion efficiency. In this work, we carried out experiments to optimize double AR coating layer with silicon nitride and silicon oxide for the silicon solar cells. The p-type mono crystalline silicon wafers with $156{\times}156mm^2$ area, 0.5-3 ${\Omega}{\cdot}cm$ resistivity, and $200{\mu}m$ thickness were used. All wafers were textured in KOH solution, doped with $POCl_3$ and removed PSG before ARC process. The optimized thickness of each ARC layer was calculated by theoretical equation. For the double layer of AR coating, silicon nitride layer was deposited first using $SiH_4$ and $NH_3$, and then silicon oxide using $SiH_4$ and $N_2O$. As a result, reflectance of $SiO_2/SiN_x$ layer was lower than single $SiN_x$ and then it resulted in increase of short-circuit current and conversion efficiency. It indicates that the double AR coating layer is necessary to obtain the high efficiency solar cell with PECVD already used in commercial line.

• 자원리싸이클링
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• 제22권2호
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• pp.22-28
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• 2013

실리콘 슬러지로부터 원심분리에 의해 1 단계로 실리콘(Si)을 분리 한 후 남게 되는 실리콘 카바이드(SiC) 농축물 내에 포함되어 있는 철과 잔존하는 실리콘을 추가적으로 제거함으로써 실리콘 카바이드의 순도를 향상 시킬 수 있는 가능성을 탐색해 보았다. 실리콘 카바이드 농축물을 대상으로 하여 염산(HCl)/수산화나트륨(NaOH)에 의한 액상 침출법과 염소 가스에 의한 기상 염소화법을 비교해 보았다. 실리콘 카바이드 농축물을 1 M 염산 수용액에서 $80^{\circ}C$에서 1 시간 동안 침출시킴으로써 회수된 실리콘 카바이드에 잔류하는 철의 농도를 49 ppm 까지 제거하였으며, 1 M 수산화나트륨 수용액에서 $50^{\circ}C$에서 1 시간 동안 침출시킴으로써 실리콘 카바이드 내 잔류하는 실리콘의 농도를 860 ppm 까지 제거하였다. 기상 염소화 반응은 직경 2.4 cm, 길이 32 cm의 전기로에 의해 가열되는 알루미나 튜브의 중심에 실리콘 카바이드 농축물을 위치시키고, 질소와 염소의 혼합가스를 흘려보내는 방식에 의해 이루어졌는데, 반응온도 $500^{\circ}C$, 반응시간 4 시간, 가스유량 300 cc/min, 염소 몰분율 10%의 조건 하에서 실리콘 카바이드 내 철과 실리콘의 잔류 농도를 48 ppm과 405 ppm 까지 낮출 수 있었다.

• 한국전기전자재료학회논문지
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• 제21권1호
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• pp.1-4
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• 2008

The electrical characteristics of polycrystalline silicon (poly-Si) thin film transistor (TFT) crystallized by excimer laser annealing (ELA) method were evaluated, The polycrystalline silicon thin-film transistor (poly-Si TFT) has higher electric field-effect-mobility and larger drivability than the amorphous silicon TFT. However, to poly-Si TFT's using conventional processes, the temperature must be very high. For this reason, an amorphous silicon film on a buried oxide was crystallized by annealing with a KrF excimer laser (248 nm)to fabricate a poly-Si film at low temperature. Then, High permittivity $HfO_2$ of 20 nm as the gate-insulator was deposited by atomic layer deposition (ALD) to low temperature process. In addition, the solid phase crystallization (SPC) was compared to the ELA method as a crystallization technique of amorphous-silicon film. As a result, the crystallinity and surface roughness of poly-Si crystallized by ELA method was superior to the SPC method. Also, we obtained excellent device characteristics from the Poly-Si TFT fabricated by the ELA crystallization method.