• Proceedings of the KIEE Conference
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• 2008.10a
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• pp.161-162
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• 2008

본 논문에서는 820.11n 규격에 적합한 Fractional-N 주파수 합성기를 설계하였다. 본 논문에서 설계한 주파수 합성기의 특징은 PFD(Phase Frequency Detector) 뒷단에 잔여 펄스를 제거하는 Pulse Remover를 연결하여 이중 궤환 Charge Pump의 안정도를 향상시켰으며, Charge Pump에서 동시에 발생하는 Up/Down 전류로 인한 Spike성 전류를 없앰으로서 스퓨리어스를 최소화 시켰다. Pulse Removed RFD를 사용함으로서 발생하는 PFD Deadzon문제는 2N+2분주와 2N-2분주기를 3차의 ${\Delta}{\Sigma}$ Modulator가 선택해줌으로 해결하였다. 삼성 0.18u 공정을 이용하여 설계 하였으며 각 블록은 Cadence spectre를 이용하여 검증하였다.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1386-1388
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• 2008

본 논문에서는 820.11n 규격에 적합한 Fractional-N 주파수 합성기를 설계하였다. 본 논문에서 설계한 주파수 합성기의 특징은 PFD(Phase Frequency Detector) 뒷단에 잔여 펄스를 제거하는 Pulse Remover를 연결하여 이중 궤환 Charge Pump의 안정도를 향상시켰으며, Charge Pump에서 동시에 발생하는 Up/Down 전류로 인한 Spike성 전류를 없앰으로서 스퓨리어스를 최소화 시켰다. Pulse Removed PFD를 사용함으로서 발생하는 PFD Deadzon문제는 2N+2분주와 2N-2분주기를 3차의 ${\Delta}{\Sigma}$ Modulator가 선택해줌으로 해결하였다. 삼성 0.18u 공정을 이용하여 설계 하였으며 각 블락은 Cadence spectre 를 이용하여 검증하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.43-51
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• 2013

This paper presents a design and implementation of a low power switched-capacitor 3rd-order delta-sigma modulator for a digital hearing-aid application. The power consumption is reduced by minimizing the output swing of integrators through optimizing the coefficients of modulator architecture and using class-AB output operational amplifiers. The modulator was implemented in a 130nm CMOS technology, and measured to have 79dB of SNR(Signal-to-Noise Ratio) in the signal bandwidth between 100Hz and 10kHz with an oversampling ratio of 160. The power consumption was $60{\mu}W$ from 1.2V power supply and the modulator core occupied $0.53mm{\times}0.53mm$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.5
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• pp.335-342
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• 2022

In this paper, a single-bit 3rd-order feedforward delta sigma modulator is proposed for audio applications. The proposed modulator is based on a class-C inverter for low voltage and power applications. For the high-precision requirement, the class-C inverter with regulated cascode structure increases its DC gain and acts as a low-voltage subthreshold amplifier. The proposed Class-C inverter-based modulator is designed and simulated in 180-nm CMOS process. With no performance loss and a low supply voltage compatibility, the proposed class-C inverter-based switched-capacitor modulator achieves high power efficiency. This design achieves an signal-to-noise-and-distortion ratio (SNDR) of 93.9 dB, an signal-to-noise ratio (SNR) of 108 dB, an spurious-free dynamic range (SFDR) of 102 dB, and a dynamic range (DR) of 102 dB at a signal bandwidth of 20 kHz and a sampling frequency of 4 MHz, while only using 280 μW of power consumption from a 0.8-V power supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.6
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• pp.706-715
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• 2012

Electro-optical sigma-delta modulators are the core module of digital receiver to digitize wideband radio-frequency signals directly at an antenna. Electro-optical sigma-delta modulators use a pulsed laser to oversample an input radio-frequency signals at two Mach-Zehnder Interferometer(MZI) and shape the quantization noise using a fiber-lattice accumulator. Decimation filtering is applied to the quantizer output to construct the input signal with high resolution. The jitter affects greatly on reconstructing the original input signal of modulator. This paper analyzes the performance of first order single bit electro-optical sigma-delta modulator in the time domain and the frequency domain. The performance of modulator is analyzed by using asynchronous spectral averaging of the reconstructed signal's spectrum in the frequency domain. The reference value of time jitter is presented by analyzing the performance of jitter effects. This kind of jitter value can be used as a reference value on the design of modulators.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.342-348
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• 2015

This paper presents a 1.9-GHz digital ${{\Delta}{\Sigma}}$ fractional-N PLL with a finite impulse response (FIR) filter embedded for noise suppression. The proposed digital implementation of FIR provides a simple method of increasing the number of taps without complicated calculation for gain matching. This work demonstrates 32 tap FIR filtering for the first time and successfully filtered the in-band phase noise generated from delta-sigma modulator (DSM). Design considerations are also addressed to find the optimum number of taps when the resolution of time-to-digital converter (TDC) is given. The PLL, fabricated in $0.11-{\mu}m$ CMOS, achieves a well-regulated in-band phase noise of less than -100 dBc/Hz for the entire range inside the bandwidth of 3 MHz. Compared with the conventional dual-modulus division, the proposed PLL shows an overall noise suppression of about 15dB both at in-band and out-of-band region.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1998.06a
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• pp.1176-1179
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• 1998

• The Magazine of the IEIE
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• v.31 no.9
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• pp.32-41
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• 2004

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.437-438
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• 2008

This paper proposes a 8th-order single loop band-pass sigma-delta modulator that satisfies a wide bandwidth of 6MHz, which is required for a HDTV application. The proposed architecture is based on a simple analog structure that enlarges the noise shaping with a low OSR. In addition, a feedforward scheme is used to relax op-amp performance requirements. The proposed modulator has been simulated using the 0.18um 1.8v TSMC technology. The simulation results show that the bandwidth is 6MHz and SNQR is 70dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.28-36
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• 2008

This paper discusses theimplementation of the low-voltage, low-power, third-order, 1-bit switched capacitor delta-sigma modulator of the implantable cardiac pacemaker. The distributed, feed-forward structure and bulk-driven OTA were used in order to achieve an efficient operation under a supply voltage of 1V or lower. The designed modulator has a dynamic range of 49dB at 0.9V supply voltage and consumes 816nW of power. Such a significant reduction in power consumption allows diverse applications, not only in pacemakers, but also in implantable biomedical devices that operate with limited battery power. The core chip size of the modulator is $1000{\mu}m*500{\mu}m$ manufactured, with the $0.18{\mu}m$ CMOS standard process.