• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• 제어로봇시스템학회:학술대회논문집
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• 1988.10a
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• pp.370-373
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• 1988

Althouah there have been many attempts to control weld quality in resistance spot welding processes, design method for an on-line feedback controller based upon process dynamics has not been suggested. This is due to the fact that the resistance spot welding is a highly complicated process, whice involves the interaction of electrical, thermal, mechanical and metallurgical phenomena. In this paper, an optimal control method based on FDM model with shunt effect is presented, which can regulate the nugget size, at the same time minimizing the control heat input. Optimal PI gain of the controller were determined by numerical optimization. Simulation results show that, as a result of the proposed optimal control, the weld nugget can be made to approach a desired nugget size with less control heat input than that required for the conventional spot welding process in the face of the shunt effect.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.319-322
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• 1998

A 20 GHz 2-stage MMIC (Monolithic Microwave Integrated Circuits) LNA(Low Noise Amplifiers) has been designed. The pHEMT with gate length of 1.15 um has been used to provide ultra low noise and high gain amplification. Series and Shunt feedback circuits were interted to ensured high stability over frequency range of DC to 60 GHz. The size of designed MMIC LNA is 2285um x 2000um(4.57mm2). The simulated noise figure of MMIC LNA is less than 1.7 dB over frequency range of 20 GHz to 21 GHz.

• Journal of the Korean Institute of Telematics and Electronics
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• v.11 no.3
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• pp.1-14
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• 1974

The gain stability of the nuclear pulse linear amplifiers with feedback for such a fast pulse input as the step voltage or the nuclear radiation detector pulse is analysed in detail. The expression is derived which describes the waveform at the anode circuit of the photomultiplier tube which is a part of the nuclear radiation detector. It is analysed and compared when the feedback amplifier has one and two time-constants. When these fast input pulse voltages are applied to the feedback amplifier, the effects of feedback in linearity and stability of the output voltage appear only after two or three rise-times of the amplifier, And it is proved that in order to reduce this limitation, the rise time of the feedback amplifier shou1d be less than the input pulse width. It is also shown that the above theory can be applied directly to the voltage-shunt feedback amplifier stages designed as the basic amplifier of the linear amplifier, and that the gain stability is more improved for the smaller input impedance of this amplifier stage.

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.310-312
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• 1994

A partial shunt regulator (PSR) which is the power regulator of KOREASAT is modeled. The modeling of the PSR consist of solar array, power circuit, controller. and load models. To realize simple structure. a voltage source of the PSR controller is used the output voltage of the PSR. The model of the PSR has very complex structure with two additional coupled feedback loops. The complex model is simplified to a simple meaningful model with only main feedback control loop. The proposed model is compared to a PSR model with DC voltage source at the PSR controller. The proposed PSR model is verified by comparing the model with SPICE simulation for small signal analysis.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.34-40
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• 2011

This paper presents a low-dropout (LDO) linear regulator using ultra-low output impedance buffer for frequency compensation. The proposed buffer achieves ultra low output impedance with dual shunt feedback loops, which makes it possible to improve load and line regulations as well as frequency compensation for low voltage applications. A reference control scheme for programmable output voltage of the LDO linear regulator is presented. The designed LDO linear regulator works under the input voltage of 2.5~4.5V and provides up to 300mA load current for an output voltage range of 0.6~3.3V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.1
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• pp.68-73
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• 2002

This paper presents the implementation of wide-band RFIC amplifier operating from near 50 MHz to 3 GHz using Tachyonics SiGe HBT foundry. Voltage shunt feedback is used for the flat gain and the broad band impedance matching. Initial design parameters are calculated through the low frequency small signal analysis. Since the HBT model was not available at the design time, discrete tuning board was made for fine adjustment in the low frequency range. Fabricated amplifier shows 12 dB gain with 1 dB fluctuation and P1 dB reaches 15 dBm at 850 MHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.443-450
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• 2014

This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 $dB{\Omega}$ and 12 GHz, respectively. 20-Gb/s $2^{31}-1$ electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than $10^{-12}$. The receiver circuit has chip area of $0.5mm{\times}0.44mm$ and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.

• Journal of Power Electronics
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• v.9 no.4
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• pp.654-666
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• 2009

Direct torque control (DTC) of induction machines (IM) is a well-known strategy of these drives control which has a fast dynamic and a good tracking response. In this paper a nonlinear DTC of speed sensorless IM drives is presented which is based on input-output feedback linearization control theory. The IM model includes iron losses using a speed dependent shunt resistance which is determined through some effective experiments. A stator flux vector is estimated through a simple integrator based on stator voltage equations in the stationary frame. A novel method is introduced for DC offset compensation which is a major problem of AC machines, especially at low speeds. Rotor speed is also determined using a rotor flux sliding-mode (SM) observer which is capable of rotor flux space vector and rotor speed simultaneous estimation. In addition, stator and rotor resistances are estimated using a simple but effective recursive least squares (RLS) method combined with the so-called SM observer. The proposed control idea is experimentally implemented in real time using a FPGA board synchronized with a personal computer (PC). Simulation and experimental results are presented to show the capability and validity of the proposed control method.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.586-590
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• 2001

In this paper, a novel control scheme compensating source voltage unbalance and harmonic currents for hybrid active power filters is proposed, where no low/high-pass filters are used in compensation voltage composition. The phase angle and compensation voltages for source harmonic current and unbalanced voltage components are derived from the positive sequence component of the unbalanced voltage set, which is simply obtained by using digital all-pass filters. Since a balanced set of the source voltage obtained by scaling the positive sequence components is used as reference values for source current and load voltage, it is possible to eliminate the necessity of low/high-pass filters in the reference generation. Therefore the control algorithm is much simpler and gives more stable performance than the conventional method. In addition, the source harmonic current is eliminated by compensating for the harmonic voltage of the load side added to feedback control of the fundamental component.