• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1181-1184
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• 2003

This paper proposes a new Sense Amplifier for MRAM. Current Sense Amplifier employs a latch-type circuit to amplify a signal from the selected memory cell. The proposed Sense Amplifier simplifies the circuit by amplifying the signal using cross-coupled PMOS transistors. It shows the same operation speed as the latch-type Sense Amplifier in simulation and occupies only 85% of the area taken by the latch-type Sense Amplifier.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.31-38
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• 2016

A novel self-reference sense amplifier with parallel reading during writing operation is proposed. Read access time is improved compared to conventional self-reference scheme with fast operation speed by reducing operation steps to 1 for read operation cycle using parallel reading scheme, while large sense margin competitive to conventional destructive scheme is obtained by using self-reference scheme. The simulation was performed using standard $0.18{\mu}m$ CMOS process. The proposed self-reference sense amplifier improved not only the operation speed of less than 20 ns which is comparable to non-destructive sense amplifier, but also sense margin over 150 mV which is larger than conventional sensing schemes. The proposed scheme is expected to be very helpful for engineers for developing MRAM technology.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.469-472
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• 2004

In this paper a current mode sense amplifier suitable for 30nm SONOS flash memories read operation is presented. The proposed sense amplifier employs cross coupled latch type circuit and current mirror to amplify signal from selected memory cell. This sense amplifier provides fast response in low voltage and low current dissipation. Simulation results show the sensing delay time and current dissipation for power supply voltages Vdd to expose limitations of the sense amplifier in various operating conditions.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.727-730
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• 2005

In this paper, we propose a new current sense amplifier for low-voltage, high-speed SRAM. As a supply voltage is reduced, a sensing delay is increased owing to reduced cell read current. It causes a low-speed operation in SRAM. To overcome this problem, we present a new current sense amplifier which consists of the current-mirror type circuit with feedback structure. For demonstration, a 0.8-V, 256-Kb SRAM incorporating the proposed current sense amplifier has been designed with $0.18-{\mu}m$ CMOS technology. The simulation results show 15.6ns of the sensing delay reduction in comparison with a previous current sense amplifier and 11.5ns of the sensing delay reduction in comparison with a voltage sense amplifier.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.538-541
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• 1998

This paper describes the development of 5.15ns 32kb asynchronous CMOS SRAM using 0.6.mu.m CMOS technology. The proposed high speed embedded SRAM is realized with optimized control circuit and sense amplifier at a power supply of 3V. Using proposed control circuit, the delay time from address input to wordline 'on' is reduced by 33% and mismatch-insensitive sense amplifier can sense a small difference of bit-line voltage fast and stably.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.526-529
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• 1998

This paper describes new sense amplifier with fast sensing delay time of 0.54ns and 32kb CMOS embedded SRAM with 4.67ns access time for a 3-V powr supply. It was achieved using the sense amplifier with multiple point sensing scheme and high speed bit-line scheme. The sense amplifier saves 25% of the power dissipation compared with the conventional one while maintaining a very short sensing delay. The SRAM uses 0.5.mu.m double-polysilicon and triplemetal CMOS process technology. A die size is 1.78mm*2.13mm.

• Journal of Electrical Engineering and information Science
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• v.3 no.3
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• pp.300-305
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• 1998

This paper describes new sense amplifier with fast sensing delay time of 0.54ns and 32kb CMOS embedded SRAM with 4.67 ns access time for a 3-V power supply. It was achieved using the sense amplifier with multiple point sensing scheme and highs peed bit-line scheme. The sense amplifier saves 25% of the power dissipation compared with the conventional one while maintaining a very short sensing delay. The SRAM uses 0.5m double-polysilicon and triple-metal CMOS process technology. A die size is 1.78${\times}$mm2.13mm.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1555-1557
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• 2002

We have investigated the precharge type sense amplifier, it is suitable fur voltage sensing in a NOR type single transistor ferroelectric field effect transistor (1T FeFET) memory read operation. The proposed precharge type sense amplifier senses the bit line voltage of 1T FeFET memory. Therefore, the reference celt is not necessary compared to current sensing in 1T FeFET memory, The high noise margin is wider than the low noise margin in the first inverter because requires tile output of precharge type sense amplifier high sensitivity to transition of input signal. The precharge type sense amplifier has very simple structure and can sense the bit line signal of the 1T FeFET memory cell at low voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.63-67
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• 2003

This paper proposes a new BLSA(Bit Line Sense Amplifier) for MRAM. Current BLSA employs a latch-type circuit to amplify a signal from the selected memory cell. The proposed BLSA simplifies the circuit by amplifying the signal using cross-coupled PMOS transistors. It shows the same operation speedas the latch-type BLSA in simulation and occupies only 85% of the area taken by the latch-type BLSA.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.87-89
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• 2006

This paper proposes a sense amplifier with non-volatile memory in order to improve the image quality of LCD by enhancing the matching of the driving voltages between the panel and driver. The sense amplifier having a wide sensing margin and fast response adjusts LCD driver voltage of display driver. The CSTN-LCD with the sense amplifier results improved image quality than that with conventional 6 bit column driver without it.