• Korean Chemical Engineering Research
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• v.47 no.1
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• pp.1-10
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• 2009

As a demand for the portable device requiring smaller size and better performance is in hike, reducing the size of conventionally used planar 2 dimensional chip cannot be a solution for the enhancement of the semiconductor chip technology due to an increase in RC delay among interconnects. To address this problem, a new technology - "3 dimensional (3D) IC chip stack" - has been emerging. For the integration of the technology, several new key unit processes (e.g., silicon through via, wafer thinning and wafer alignment and bonding) should be developed and much effort is being made to achieve the goal. As a result of such efforts, 4 and 8 chip-stacked DRAM and NAND structures and a system stacking CPU and memory chips vertically were successfully developed. In this article, basic theory, configurations and key unit processes for the 3D IC chip integration, and a current tendency of the technology are explained. Future opportunities and directions are also discussed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.5
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• pp.515-520
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• 2004

We report on the development of a Piezoelectric valvc that is designed to have a high reliability for fluid control systems, such as mass flow control, transportation and chemical analysis. The valve was fabricated using a MCA(multilayer ceramic actuator), which has a low consumption power, high resolution and accurate control. The fabricated valve is composed of MCA, a valve actuator die and an seat die. The design of the actuator dic was done by FEM(finite element method) modeling, respectively. And, the valve seat die with 6 trenches was made. and the actuator die, which possible to optimize control to MCA, was fabricated. After Si-wafer direct bonding between the seat die and the actuator die, MCA was also anodic bonded to the scat/actuator die structure. PDMS(poly dimethylsiloxane) sealing pad was fabricated to minimize a leak-rate. It was also bonded to scat die and stainless steel package. The flow rate was 9.13 sccm at a supplied voltage of 100 V with a 50 % duty ratio and non-linearity was 2.24 % FS. From these results, the fabricated MCA valve is suitable for a variety of flow control equipments, a medical bio-system, semiconductor fabrication process, automobile and air transportation industry with low cost, batch recess and mass production.

• Korean Journal of Materials Research
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• v.23 no.10
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• pp.580-585
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• 2013

To observe the formation of defects at the interface between an oxide semiconductor and $SiO_2$, ZnO was prepared on $SiO_2$ with various oxygen gas flow rates by RF magnetron sputtering deposition. The crystallinity of ZnO depends on the characteristic of the surface of the substrate. The crystallinity of ZnO on a Si wafer increased due to the activation of ionic interactions after an annealing process, whereas that of ZnO on $SiO_2$ changed due to the various types of defects which had formed as a result of the deposition conditions and the annealing process. To observe the chemical shift to understand of defect deformations at the interface between the ZnO and $SiO_2$, the O 1s electron spectra were convoluted into three sub-peaks by a Gaussian fitting. The O 1s electron spectra consisted of three peaks as metal oxygen (at 530.5 eV), $O^{2-}$ ions in an oxygen-deficient region (at 531.66 eV) and OH bonding (at 532.5 eV). In view of the crystallinity from the peak (103) in the XRD pattern, the metal oxygen increased with a decrease in the crystallinity. However, the low FWHM (full width at half maximum) at the (103) plane caused by the high crystallinity depended on the increment of the oxygen vacancies at 531.66 eV due to the generation of $O^{2-}$ ions in the oxygen-deficient region formed by thermal activation energy.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.55-59
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• 2018

In this paper, we investigated the characteristics of shear stress type piezoresistor on a diaphragm structure formed by MEMS (Microelectromechanical System) technology of silicon-direct-bonding (SDB) wafers with Si/$SiO_2$/Si-sub. The diaphragm structure formed by etching the backside of the wafer using a TMAH aqueous solution can be used for manufacturing various sensors. In this study, the optimum shape condition of the shear stress type piezoresistor formed on the diaphragm is found through ANSYS simulation, and the diaphragm structure is formed by using the semiconductor microfabrication technique and the shear stress formed by boron implantation. The characteristics of the piezoelectric resistance are compared with the simulation results. The sensing diaphragm was made in the shape of an exact square. It has been experimentally found that the maximum shear stress for the same pressure at the center of the edge of the diaphragm is generated when the structure is in the exact square shape. Thus, the sensing part of the sensor has been designed to be placed at the center of the edge of the diaphragm. The prepared shear stress type piezoresistor was in good agreement with the simulation results, and the sensitivity of the piezoresistor formed on the $2200{\mu}m{\times}2200{\mu}m$ diaphragm was $183.7{\mu}V/kPa$ and the linearity of 1.3 %FS at the pressure range of 0~100 kPa and the symmetry of sensitivity was also excellent.

• Journal of the Korea Organic Resources Recycling Association
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• v.31 no.1
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• pp.35-45
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• 2023

In this study, the sludge formation in the wastewater drain from the advanced packaging process mechanisms are revealed as well as the key factors, materials, and sludge prevention methods using surfactant. Compared with that of conventional packaging process, advanced packaging process employ similar process to the semiconductor fabrication process, and thus many processes may generate wastewater. In specific, a large amount of wastewater may generate during the carrier wafer bonding, photo, development, and carrier wafer debonding processes. In order to identify the key factors for the formation of sludge during the advanced packaging process, six types of chemicals including bonding glue, HMDS, photoresist (PR), PR developer, debonding cleaner, and water are utilized and mixing evaluation is assessed. As a result, it is confirmed that the black solid sludge is formed, which is originated by the sludge seed formation by hydrolysis/dehydration reaction of HMDS and sludge growth via hydrophobic-hydrophobic binding with sludge seed and PR. For the sludge prevention investigation, three surfactants of CTAB, PEG, and shampoo are mixed with the key materials of sludge, and it is confirmed that the sludge formations are successfully suppressed. The underlying mechanism behind the sludge formation is that the carbon tails of the surfactant bind to PR with hydrophobic-hydrophobic interaction and inhibit the reaction with HMDS-based slurry seeds to prevent the sludge formation. In this regard, it is expected that various problems like clogging in drains and pipes during the advanced packaging process may effectively solve by the injection of surfactants into the drains.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.3
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• pp.661-669
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• 1999

A probe card is one of the most important pan of test systems as testing IC(integrated circuit) chips. This work was related to bump-type silicon vertical probe card which enabled simultaneous tests for multiple semiconductor chips. The probe consists of silicon cantilever with bump tip. In order to obtain optimum size of the cantilever, the dimensions were determined by FEM(finite element method) analysis. The probe was fabricated by RIE(reactive ion etching), isotropic etching, and bulk-micromachining using SDB(silicon direct bonding) wafer. The optimum height of the bump of the probe detemimed by FEM simulation was 30um. The optimum thickness, width, and length of the cantilever were 20 $\mum$, 100 $\mum$,and 400 $\mum$,respectively. Contact resistance of the fabricated probe card measured at contact resistance testing was less than $2\Omega$. It was also confirmed that its life time was more than 20,000 contacts because there was no change of contact resistance after 20,000 contacts.