• Journal of Korean Institute of Industrial Engineers
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• v.28 no.4
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• pp.415-424
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• 2002

Semiconductor manufacturing has been emerged as a highly competitive but profitable business. Accordingly it becomes very important for semiconductor manufacturing companies to meet customer demands at the right time, in order to keep the leading edge in the world market. However, due-date oriented production is very difficult task because of the complex job flows with highly resource conflicts in fabrication shop called FAB. Due to its cyclic manufacturing feature of products, to be completed, a semiconductor product is processed repeatedly as many times as the number of the product manufacturing cycles in FAB, and FAB processes of individual manufacturing cycles are composed with similar but not identical unit processes. In this paper, we propose a production scheduling and control scheme that is designed specifically for semiconductor scheduling environment (FAB). The proposed scheme consists of three modules: simulation module, cycle due-date estimation module, and dispatching module. The fundamental idea of the scheduler is to introduce the due-date for each cycle of job, with which the complex job flows in FAB can be controlled through a simple scheduling rule such as the minimum slack rule, such that the customer due-dates are maximally satisfied. Through detailed simulation, the performance of a cycle due-date based scheduler has been verified.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.39 no.1
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• pp.153-161
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• 2016

Semiconductor manufacturing has suffered from the complex process behavior of the technology oriented control in the production line. While the technological processes are in charge of the quality and the yield of the product, the operational management is also critical for the productivity of the manufacturing line. The fabrication line in the semiconductor manufacturing is considered as the most complex part because of various kinds of the equipment, re-entrant process routing and various product devices. The efficiency and the productivity of the fabrication line may give a significant impact on the subsequent processes such as the probe line, the assembly line and final test line. In the management of the re-entrant process such as semiconductor fabrication, it is important to keep balanced fabrication line. The Performance measures in the fabrication line are throughput, cycle time, inventory, shortage, etc. In the fabrication, throughput and cycle time are the conflicting performance measures. It is very difficult to achieve two conflicting goal simultaneously in the manufacturing line. The capacity of equipment is important factor in the production planning and scheduling. The production planning consideration of capacity can make the scheduling more realistic. In this paper, an input and scheduling rule are to achieve the balanced operation in semiconductor fabrication line through equipment capacity and workload are proposed and evaluated. New backward projection and scheduling rule consideration of facility capacity are suggested. Scheduling wafers on the appropriate facilities are controlled by available capacity, which are determined by the workload in terms of the meet the production target.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.6
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• pp.724-733
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• 1999

An effective method of system modeling and dynamic scheduling for the back-end line of semiconductor manufacturing is proposed. The virtual factory, describing semiconductor manufacturing line, is designed in detail, and then a Petri net model simulator is developed for operation and control of the modular cells of the virtual factory. The petri net model is a colored timed Petri nets (CTPNs). The simulator will be utilized to analyze and evaluate various dynamic status and operatons of manufacturing environments. The dynamic schedulaer has a hierarchical structure with the higher for planning level and the lower for dynamic scheduling level. The genetic algorithm is applied to extract optimal conditions of the scheduling algorithm. The proposed dynamic scheduling is able to realize the semiconductor manufacturing environments for the diversity of products, the variety of orders by many customers, the flexibility of order change by changing market conditions, the complexity of manufacturing processes, and the uncertainty of manufacturing resources. The proposed method of dynamic scheduling is more effective and useful in dealing with such recent pressing requirements including on-time delivery, quick response, and flexibility.

• Journal of the Korea Society for Simulation
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• v.19 no.3
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• pp.45-54
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• 2010

The inherent complexity of semiconductor fabrication processes makes it hard to solve well-known job scheduling problems in analytical ways, which leads us to rely practically on discrete event modeling simulations to learn the effects of changing the system's parameters. Meanwhile, unpredictable disturbances such as machine failures and maintenance diminish the productivity of semiconductor manufacturing processes with fixed scheduling policies; thus, it is necessary to adapt job scheduling policy in a timely manner in reaction to critical environmental changes (disturbances) in order for the fabrication process to perform optimally. This paper proposes an adaptive job control framework for a wafer fabrication process in a control system theoretical approach and implements it based on a DEVS modeling simulation environment. The proposed framework has the advantages in view of the whole systems understanding and flexibility of applying new rules compared to most ad-hoc software approaches in this field. Furthermore, it is flexible enough to incorporate new job scheduling rules into the existing rule set. Experimental results show that this control framework with adaptive rescheduling outperforms fixed job scheduling algorithms.

• IE interfaces
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• v.12 no.3
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• pp.437-447
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• 1999

Modeling and system development for the fabrication process in the semiconductor manufacturing is presented in this paper. Maximization of wafer production can be achieved by the wafer flow balance under high utilization of bottleneck machines. Relatively simpler model is developed for the fabrication line by considering main characteristics of logistics. Simulation system is developed to evaluate the line performance such as balance rate, utilization, WIP amount and wafer production. Scheduling rules and input rules are suggested, and tested on the simulation system. We have shown that there exists good combination of scheduling and input rules.

• Journal of Korean Institute of Industrial Engineers
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• v.36 no.2
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• pp.125-137
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• 2010

This study focuses on the problem of scheduling wafer lots of several product families in the deposition workstation in a semiconductor wafer fabrication facility. There are multiple identical parallel machines in the deposition workstation, and two types of setups, record-dependent setup and family setup, may be required at the deposition machines. A record-dependent setup is needed to find optimal operational conditions for a wafer lot on a machine, and a family setup is needed between processings of different families. We suggest two-phase heuristic algorithms in which a priority-rule-based scheduling algorithm is used to generate an initial schedule in the first phase and the schedule is improved in the second phase. Results of computational tests on randomly generated test problems show that the suggested algorithms outperform a scheduling method used in a real manufacturing system in terms of the sum of weighted flowtimes of the wafer lots.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.4
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• pp.692-699
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• 2008

Semiconductor research and development(R&D) fabs are very different than production fabs in many ways such as the scales of production, job priority, production methods, and performance measures. Efficient operations of R&D fabs are very important to the development of new product, process stability, high yield, and ultimately company competitiveness. This paper proposes the fab-wide scheduling method for operational optimization of the R&D fabs. Most scheduling systems of semiconductor fabs have only focused on maximizing throughput of each separated areas without considering WIP(works in process) flows of entire fab. In this paper, we proposes the a fab-wide scheduling system which schedules all lots to entire fab equipment at once. We develop the MIP(mixed integer programing) model which allocates the lots to production equipment considering many constraints of all processes and the CP(constraint programming) model which determines the sequences of the lots in the production equipment. The proposed FAB-wide scheduling model is applied to the newly constructed R&D fab. As a result, we have accomplished the system based automated job reservation, decrease of the hot lot delay, increase of the queue time satisfaction, the high throughput by maximizing the batch sizes, decrease of the WIP TAT(Turn Around Time).

• Industrial Engineering and Management Systems
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• v.12 no.4
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• pp.306-316
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• 2013

The semiconductor industry has grown rapidly, and subsequently production planning problems have raised many important research issues. The reentrant flow-shop (RFS) scheduling problem with time windows constraint for harddisk devices (HDD) manufacturing is one such problem of the expanded semiconductor industry. The RFS scheduling problem with the objective of minimizing the makespan of jobs is considered. Meeting this objective is directly related to maximizing the system throughput which is the most important of HDD industry requirements. Moreover, most manufacturing systems have to handle the quality of semiconductor material. The time windows constraint in the manufacturing system must then be considered. In this paper, we propose a hybrid genetic algorithm (HGA) for improving chromosomes/offspring by checking and repairing time window constraint and improving offspring by left-shift routines as a local search algorithm to solve effectively the RFS scheduling problem with time windows constraint. Numerical experiments on several problems show that the proposed HGA approach has higher search capability to improve quality of solutions.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2001.10a
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• pp.298-301
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• 2001

In semiconductor manufacturing, wafer fabrication is the most complicated and important process, which is composed of several hundreds of process steps and several hundreds of machines involved. The productivity of the manufacturing mainly depends on how well they control balance of WIP flow to achieve maximal throughput under short manufacturing cycle time. In this paper mathematical formulation is suggested for the stepper scheduling, in which cycle time reduction and maximal production is achieved.

• Journal of Korean Institute of Industrial Engineers
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• v.21 no.3
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• pp.357-369
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• 1995

Wafer fabrication process is the most important and critical process in semiconductor manufacturing. The process is very complicated and hard to establish an efficient schedule due to its complexity. Furthermore, several performance indices such as due dates, throughput, cycle time and workstation utilizations are to be considered simultaneously for an efficient schedule, and some of these indices have negative correlations in performances each other. We develop an efficient heuristic scheduling algorithm; Hybrid Input Control Policy and Hybrid Dispatching Rule. Through numerical experiments, it is shown that the proposed Hybrid Scheduling Algorithm gives better performance compared with existing algorithms.