Browse > Article

The Operational Optimization of Semiconductor Research and Development Fabs by FAB-wide Scheduling  

Kim, Young-Ho (성균관대 정보통신 공학부)
Lee, Jee-Hyong (성균관대)
Sun, Dong-Seok (삼성전자)
Publication Information
The Transactions of The Korean Institute of Electrical Engineers / v.57, no.4, 2008 , pp. 692-699 More about this Journal
Abstract
Semiconductor research and development(R&D) fabs are very different than production fabs in many ways such as the scales of production, job priority, production methods, and performance measures. Efficient operations of R&D fabs are very important to the development of new product, process stability, high yield, and ultimately company competitiveness. This paper proposes the fab-wide scheduling method for operational optimization of the R&D fabs. Most scheduling systems of semiconductor fabs have only focused on maximizing throughput of each separated areas without considering WIP(works in process) flows of entire fab. In this paper, we proposes the a fab-wide scheduling system which schedules all lots to entire fab equipment at once. We develop the MIP(mixed integer programing) model which allocates the lots to production equipment considering many constraints of all processes and the CP(constraint programming) model which determines the sequences of the lots in the production equipment. The proposed FAB-wide scheduling model is applied to the newly constructed R&D fab. As a result, we have accomplished the system based automated job reservation, decrease of the hot lot delay, increase of the queue time satisfaction, the high throughput by maximizing the batch sizes, decrease of the WIP TAT(Turn Around Time).
Keywords
FAB-wide scheduler; Hot lot; Batch size; System based tracking; Queue time constraint;
Citations & Related Records

Times Cited By SCOPUS : 0
연도 인용수 순위
  • Reference
1 Lee, K.H., Hong, Y.S., and Kim, S.Y. (1995), Production Scheduling in Semiconductor Wafer Fabrication Process, Journal of the Korean Institute of Industrial Engineers, 21, 357-469
2 Lee, Y.H., Park, J.K. and Kim, S.Y. (2002), Experimental Study on Input and Bottleneck Scheduling for a Semiconductor Fabrication Line, IIE Transactions, 34, 179-190
3 Choung, Y.I., Jun, K.S., Han, D.S. and Jang, Y.C. (2001) Design of a Scheduling System for Diffusion Process, International Conference on Semiconductor Manufacturing Operational Modeling and Simulation
4 Liao, D.Y., Pei, K.W. and Chang, C.M.(1996), Daily Scheduling for R&D Semiconductor Fabircation, IEEE Transactions on Semiconductor Manufacturing, 9(4), 550-561   DOI   ScienceOn
5 Ham, M.S. et al. (2006), Dynamic Wet-Furnace Dispatching/Scheduling in Wafer Fab, The 17th Annual SEMI/IEEE Advanced Semiconductor Manufacturing Conference
6 Leachman, R.C., Kang, J., Lin, V. (2002), SLIM: Short Cycle Time and Low Inventory in Manufacturing at Samsung Electronics, Interface, 32(1), 61-77   DOI   ScienceOn