• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.23 no.9A
• /
• pp.2197-2210
• /
• 1998

In the grand alliance (GA) HDTV receiver, a coherent detection is empolyed for coherent demodulation of vestigial side-band (VSB) signal by using frequency and phaselocked loop(FPLL) operating on the pilot carrier. Additional phase tracking loop (PTL) employed to track out phase noise that has not been removed by the FPLL in theGA system. In this paper, we propose an algorithm for phase detection which utilizes a weighting function. The simplest implementation of the proposed algorithm using te sign of the Q channel component can be tractable by imposing a phase detection gain to the loop gain. It is obserbed that the propsoed algorithm has a robust characteristic against the performance of the digital filters used for Q channel estimation. A second goal of this paper is to introduce a gain control algorithm for the PTL in order to provide an effective implementation of the proposed phase detection algorithm. And we design the PTL through the realization of the simplified digital filter for H/W reduction. The proposed algorithms and the designed PTL are evaluated by computer simulation. In spite of using the simplified H/W structure, simulation results show that the proposed algorithms outperform the coventional PTL algorithms in the phase detection and tracking performance.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.24 no.3
• /
• pp.169-180
• /
• 2019

Grid codes for grid-connected inverters are essential considerations for bulk grid systems. In particular, a low-voltage ride-through (LVRT) function, which can contribute to the grid system's stabilization with the occurrence of voltage sag, is required by such inverters. However, when the grid voltage is under zero-voltage condition due to a grid accident, a zero-voltage ride-through (ZVRT) function is required. Grid-connected inverters typically have phase-locked loop (PLL) control to synchronize the phase of the grid voltage with that of the inverter output. In this study, the LVRT regulations of Germany, the United States, and Japan are analyzed. Then, three major PLL methods of grid-connected single-phase inverters, namely, notch filter-PLL, dq-PLL using an active power filter, and second-order generalized integrator-PLL, are reviewed. The proposed PLL method, which controls inverter output under ZVRT condition, is suggested. The proposed PLL operates better than the three major PLL methods under ZVRT condition in the simulation and experimental tests.

• Journal of Power Electronics
• /
• v.18 no.6
• /
• pp.1659-1669
• /
• 2018

An improved circulating current suppression control method is proposed in this paper. In the proposed controller, an outer loop of the average capacitor voltage control model is used to balance the sub-module capacitor voltage. Meanwhile, an individual voltage balance controller and an arm voltage balance controller are also used. The DC and harmonic components of the circulating current are separated using a low pass filter. Therefore, a multiple quasi-proportional-resonant (multi-quasi-PR) controller is introduced in the inner loop to eliminate the circulating harmonic current, which mainly contains second-order harmonic but also contains other high-order harmonics. In addition, the parameters of the multi-quasi-PR controller are designed in the discrete domain and an analysis of the stability characteristic is given in this paper. In addition, a simulation model of a three-phase MMC system is built in order to confirm the correctness and superiority of the proposed controller. Finally, experiment results are presented and compared. These results illustrate that the improved control method has good performance in suppressing circulating harmonic current and in balancing the capacitor voltage.

• International Journal of Ocean System Engineering
• /
• v.1 no.4
• /
• pp.205-210
• /
• 2011

High data-rate underwater communications is demanded. This demand imposes stringent requirements on underwater communication equipment of phase-locked-loop (PLL). Phase noise in PLL is unwanted and unavoidable. In this paper, we investigate the PLL phase noise effect on high order QAM for underwater communication systems. The phase noise model using power spectral density is adopted for performance evaluation. The phase noise components considered in PLL are reference oscillator, voltage controlled oscillator (VCO), filter and divider. The filters in PLL noise are assumed to be second order active and passive low pass filters. Through simulation, we analyze the phase noise characteristics of the four components and then investigate the performance improvement factor of each component. Consequently, we derive specifications of VCO, phase detector, divider to meet performance requirement of high data-rate communication using QAM under phase noise influence.

• Proceedings of the KIEE Conference
• /
• 2006.07d
• /
• pp.1862-1863
• /
• 2006

In this paper, A new tuning method for IMC-PID controller is proposed with the identification using the relay method from closed-loop transfer function. It is considered a second-order plus delay time(SOPDT) model and selected a third-order plus delay time transfer function model as a target function. The filter function is derived from the suitable target function to satisfy the design specifications. A robustness test was done to verify the robust-stability.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.51 no.4
• /
• pp.175-185
• /
• 2002

In this paper, a new fully digital current control method of UPS inverter, which is based on an internal model control, is proposed. In the proposed control system, overshoots and oscillations due to the computation time-delay are compensated by explicit incorporation of the time-delay in the current control loop transfer function. The internal model controller is adopted to a second order deadbeat reference-to-output response which means that its response reaches the reference in two sampling time including computational time-delays. That is, the average current of filter capacitor is been exactly equal to the reference current with a time lag of two sampling intervals. Therefore, this method has an essentially overshoot free reference-to-output response with a minimum possible rise time. The effectiveness of the proposed control system has been verified by the simulation and experimental respectively. From the simulation and experimental results, the proposed system is achieved the robust characteristics to the calculation time delay and parameter variation as well as very fast dynamic performance, thus it can be effectively applied to the power supply for the critical load.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.459-460
• /
• 2008

In this paper, a 10Gbps clock and data recovery circuit is designed in $0.18{\mu}m$ CMOS technology. The circuit incorporates a multiphase LC oscillator, a quarter-rate Bang-Bang phase detector, a charge pump and a second order loop filter. The simulation results show that the designed circuit has a peak-to-peak clock jitter of 4.2ps and a peak-to-peak recovered data jitter of 8ps while consuming about 80mW from a 1.8V supply.

• Proceedings of the KIEE Conference
• /
• 2015.07a
• /
• pp.1263-1264
• /
• 2015

본 논문에서는 PDL 기반 인터리빙 가능한 2차 Solc형 광유 간섭 필터를 제안하며, 출력되는 투과 스펙트럼들을 이론적으로 분석 및 실험적으로 측정하였다. 제안된 필터에서 각각의 구성요소는 편광 빔분배기, 반파장판, 그리고 복굴절이 큰 광섬유로 이루어진다. 이전의 Solc형 2차 광섬유 필터에서 복굴절이 큰 광섬유들은 특정한 각도로 융착 결합되어 편광 제어에 한계가 있었지만, 제안된 구조에서는 복굴절이 큰 광섬유 사이 반파장판을 삽입하여 주축의 각도 및 편광 제어를 유연하게 설정하여 출력 투과 스펙트럼들의 스위칭 특성을 유도하였다.

• Proceedings of the KIEE Conference
• /
• 2007.10a
• /
• pp.197-198
• /
• 2007

In this paper, a 10Gbps Clock and Data Recovery circuit is designed in $0.18{\mu}m$ CMOS Technology. The circuit incorporates a multiphase LC oscillator, a quarter-rate Bang-Bang phase detector, a Charge Pump and a second order loop filter. The simulation results show that the designed circuit has a peak-to-peak clock jitter of 4.1ps and a peak-to-peak recovered data jitter of 8ps while consuming about 44mW from a 1.8V supply.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.15 no.5
• /
• pp.13-18
• /
• 1978

A delay switching PLL (DSPLL) is proposed for improvement of the frequency acquisition Performance (pull-in range) while keeping a narrow bandwidth LPF. It has, between the phase detector and the LPF, just a simple RC delay circuit, a switch and another phase detector controlling the switching time. For the common second order PLL, the pull-in capability of the DSPLL is analyzed approximately, without considering additive white noise effect, and verified experimentally. It is shown that the delay switching extends the pull-in range significantly, as much as a half of lock-range. At the phase tracking mode, the delay switching does not function, to make the DSPLL be a normal PLL.