Pull-in Characteristics of Delay Switching Phase-Locked Loop

Delay Switching PLL의 Pull-in 특성

A delay switching PLL (DSPLL) is proposed for improvement of the frequency acquisition Performance (pull-in range) while keeping a narrow bandwidth LPF. It has, between the phase detector and the LPF, just a simple RC delay circuit, a switch and another phase detector controlling the switching time. For the common second order PLL, the pull-in capability of the DSPLL is analyzed approximately, without considering additive white noise effect, and verified experimentally. It is shown that the delay switching extends the pull-in range significantly, as much as a half of lock-range. At the phase tracking mode, the delay switching does not function, to make the DSPLL be a normal PLL.

본 논문에서는 PLL의 pull-in 특성을 개선하기 위하여 delay switching PL난을 제시하였다. phase detector와 low grass filter사이에 간단한 RC delay회로를 삽입하고, 90° shift 시킨 Phase detector출력에 의하여 delay time을 switching하였다. 그 결과 pull-in range는 lock range의 1/2이상으로 넓힐 수 있었으며 pull-in time도 개선되었다. 이 개선된 Pull-in특성은 근사적으로 해석되었으며 실험으로 확인되었다.