• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2002년도 하계학술대회 논문집 Vol.3 No.2
• /
• pp.834-838
• /
• 2002

In this paper, we have fabricated 4H-SiC schottky diodes utilizing a metal-oxide overlap structure for electric filed termination. The barrier height and Ideality factor were measured by current-voltage, capacitance-voltage characteristics. Schottky barrier height(SBH) were 1.41ev for Ni and 1.35eV for Pt, 1.52eV for Pt/Ti at room temperature and Pt/Ti Schottky diode exhibited Ideality factor was 1.06 to 1.4 in the range of $25^{\circ}C{\sim}200^{\circ}C$. To improve the reverse bias characteristics, an edge termination technique is employed for Pt/Ti/4H-SiC Schottky rectifiers and the device show excellent characteristics with higher blocking voltage up to 780V compared with unterminated devices.

• 한국전기전자재료학회논문지
• /
• 제19권9호
• /
• pp.818-824
• /
• 2006

The effects of high-temperature process required to fabricate the SiC devices on the surface morphology and the electrical characteristics were investigated for 4H-SiC Schottky diodes. The 4H-SiC diodes without a graphite cap layer as a protection layer showed catastrophic increase in an excess current at a forward bias and a leakage current at a reverse bias after high-temperature annealing process. Moreover it seemed to deviate from the conventional Schottky characteristics and to operate as an ohmic contact at the low bias regime. However, the 4H-SiC diodes with the graphite cap still exhibited their good electrical characteristics in spite of a slight increase in the leakage current. Therefore, we found that the graphite cap layer serves well as the protection layer of silicon carbide surface during high-temperature annealing. Based on a closer analysis on electric characteristics, a conductive surface transfiguration layer was suspected to form on the surface of diodes without the graphite cap layer during high-temperature annealing. After removing the surface transfiguration layer using ICP-RIE, Schottky diode without the graphite cap layer and having poor electrical characteristics showed a dramatic improvement in its characteristics including the ideality factor[${\eta}$] of 1.23, the schottky barrier height[${\Phi}$] of 1.39 eV, and the leakage current of $7.75\{times}10^{-8}\;A/cm^{2}$ at the reverse bias of -10 V.

• 한국진공학회지
• /
• 제16권3호
• /
• pp.197-204
• /
• 2007

p-형 실리콘 기판 위에 수 ${\AA}$ 두께의 어븀 금속을 증착하고, 후열처리 과정을 통하여 어븀-실리사이드/p-형 실리콘 접합을 형성하였다. 초고진공 자외선 광전자 분광 실험을 통하여 증착한 어븀의 두께에 따라 어븀-실리사이드의 일함수가 4.1 eV까지 급하게 감소하는 것을 관찰하였으며, X-ray 회절 실험에 의하여 형성된 어븀 실리사이드가 주로 $Er_5Si_3$상으로 구성되어 있음을 밝혔다. 또한, 어븀-실리사이드/p-형 실리콘 접합에 알루미늄 전극을 부착하여 쇼트키 다이오드를 제작하고, 전류전압 곡선을 측정하여 쇼트키 장벽의 높이를 산출하였다. 산출된 쇼트키 장벽의 높이는 $0.44{\sim}0.78eV$이었으며 어븀 두께 변화에 따른 상관 관계를 찾기 어려웠다. 그리고 이상적인 쇼트키 접합을 가정하고 이미 측정한 일함수로부터 산출한 쇼트키 장벽의 높이는 전류-전압 곡선으로부터 산출한 값에 크게 벗어났으며, 이는 어븀-실리사이드가 주로 $Er_5Si_3$ 상으로 구성되어 있고, $Er_5Si_3/p-$형 실리콘 계면에 존재하는 고밀도의 계면 상태에 기인한 것으로 사료된다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제13권4호
• /
• pp.381-386
• /
• 2013

A new resistance model for a Schottky Barrier Diode (SBD) in CMOS technology is proposed in this paper. The proposed model includes the n-well thickness as a variable to explain the operational behavior of a planar SBD which is firstly introduced in this paper. The model is verified using the simulation methodology ATLAS. For verification of the analyzed model and the ATLAS simulation results, SBD prototypes are fabricated using a $0.13{\mu}m$ CMOS process. It is demonstrated that the model and simulation results are consistent with measurement results of fabricated SBD.

• 한국소음진동공학회:학술대회논문집
• /
• 한국소음진동공학회 2007년도 추계학술대회논문집
• /
• pp.77-81
• /
• 2007

Pentacene was dissolved in N-methyspyrrolidone (NMP) and mixed with poly(3,4-ethylenedioxythiophene), poly(styrenesulfonate) (PEDOT:PSS). The solution color changed from deep purple to intense yellow. As the dissolution time increased, visible absorption decreased and ultraviolet (UV) absorption increased. PEDOT:PSS or Pentacene-PEDOT:PSS was spin-coated to control the layer thickness. Three-layered Schottky diodes consisting of Al, PEDOT:PSS or PEDOT:PSS-pentacene, and Au with thickness of 300nm, respectively, were fabricated. The current densities of $4.8{\mu}A/cm^2$ at 2.5MV/m and $660{\mu}A/cm^2$ at 1.9MV/m were obtained for the Au/PEDOT:PSS/Al and Au/Pentacene-PEDOT:PSS/Al Schottky diodes, respectively. The current density of the Schottky diode was enhanced by about two orders of magnitude by doping pentacene to PEDOT:PSS.

• Transactions on Electrical and Electronic Materials
• /
• 제16권4호
• /
• pp.187-189
• /
• 2015

A charge-trap flash (CTF) thin film transistor (TFT) memory is proposed at a low-temperature process (≤ 450℃). The memory cell consists of a sputtered oxide-nitride-oxide (ONO) gate dielectric and Schottky barrier (SB) source/drain (S/D) junctions using nickel silicide. These components enable the ultra-low-temperature process to be successfully achieved with the ONO gate stacks that have a substrate temperature of room temperature and S/D junctions that have an annealing temperature of 200℃. The silicidation process was optimized by measuring the electrical characteristics of the Ni-silicided Schottky diodes. As a result, the Ion/Ioff current ratio is about 1.4×10⁵ and the subthreshold swing and field effect mobility are 0.42 V/dec and 14 cm²/V·s at a drain voltage of −1 V, respectively.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2002년도 하계학술대회 논문집
• /
• pp.350-353
• /
• 2002

High voltage SiC Schottky barrier diodes with field plate structure have been fabricated and characterized. N-type 4H-SiC wafer with an epilayer of ∼10$\^$15/㎤ doping level was used as a starting material. Various Schottky metals such as Ni, Pt, Ta, Ti were sputtered and thermally-evaporated on the low-doped epilayer. Ohmic contact was formed at the backside of the SiC wafer by annealing at 950$^{\circ}C$ for 90 sec in argon using rapid thermal annealer. Field oxide of 550${\AA}$ in thickness was formed by a wet oxidation process at l150$^{\circ}C$ for 3h and subsequently heat-treated at l150$^{\circ}C$ for 30 min in argon for improving oxide quality. The turn-on voltages of the Ni/4H-SiC Schottky diode was 1.6V which was much higher than those of Pt(1.0V), Ta(0.7V) and Ti(0.7). The voltage drop was measured at the current density of 100A/$\textrm{cm}^2$ showing 2.1V for Ni Schottky diode, 1.45V for Pt 1.35V, for Ta, and 1.25V for Ti, respectively. The maximum reverse breakdown voltage was measured 1100V in the file plated Schottky diodes with 101an thick epilayer.

• 한국재료학회:학술대회논문집
• /
• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
• /
• pp.67-67
• /
• 2003

• 한국전기전자재료학회논문지
• /
• 제31권6호
• /
• pp.362-366
• /
• 2018

Silicon carbide is widely used in power semiconductor devices owing to its high energy gap. In particular, Schottky barrier diode (SBD) and PiN diodes fabricated on 4H-SiC wafers are being applied to various fields such as power devices. The characteristics of SBD and PiN diodes can be extracted from C-V and I-V characteristics. The measured Schottky barrier height (SBH) was 1.23 eV in the temperature range of 298~473 K, and the average ideal factor is 1.17. The results show that the device with the Schottky contact is characterized by the theory of thermal emission. As the temperature increases, the parameters are changed and the Vth is shifted to lower voltages.

• 전기학회논문지
• /
• 제66권4호
• /
• pp.659-665
• /
• 2017

Power semiconductor devices required the low on-resistance and high breakdown voltage. Wide band-gap materials opened a new technology of the power devices which promised a thin drift layer at an identical breakdown voltage. The diamond had the wide band-gap of 5.5 eV which induced the low power loss, high breakdown capability, low intrinsic carrier generation, and high operation temperature. We investigated the p-type pseudo-vertical diamond Schottky barrier diodes using a numerical simulation. The impact ionization rate was material to calculating the breakdown voltage. We revised the impact ionization rate of the diamond for adjusting the parallel-plane breakdown field at 10 MV/cm. Effects of the field plate on the breakdown voltage was also analyzed. A conventional diamond Schottky barrier diode without field plate exhibited the high forward current of 0.52 A/mm and low on-resistance of $1.71{\Omega}-mm$ at the forward voltage of 2 V. The simulated breakdown field of the conventional device was 13.3 MV/cm. The breakdown voltage of the conventional device and proposed devices with the $SiO_2$ passivation layer, anode field plate (AFP), and cathode field plate (CFP) was 680, 810, 810, and 1020 V, respectively. The AFP cannot alleviate the concentration of the electric field at the cathode edge. The CFP increased the breakdown voltage with evidences of the electric field and potential. However, we should consider the dielectric breakdown because the ideal breakdown field of the diamond is higher than that of the $SiO_2$, which is widely used as the passivation layer. The real breakdown voltage of the device with CFP decreased from 1020 to 565 V due to the dielectric breakdown.