• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1492-1494
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• 1987

This paper describes a hardware architecture called Edge Painting Machine for real time generation of scan line images for raster scan graphics display. The Edge Painting Machine consists of Scanline Processor which converts polygon data sorted in their depth priority into a set of scan line commands for each scan line, and Edge Painting Tree which converts the scanline commands set into a raster line image. Edge painting tree has been designed using combinational logic circuit. The designed circuit has been simulated to verify the proper functioning. A salient feature of the EPT is that hardware composition is simple, because each processor is constituted by only combinational logic circuit.

• 대한의용생체공학회:의공학회지
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• 제5권1호
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• pp.85-92
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• 1984

A new architecture of the Digital Scan Converter (DSC) for the linear-scan ultrasound medical imaging systems is proposed and its hardware implementation is reported. While the conventional DSC merely displays the acquisited data and does nor allow access to the frame memory, it is possible, in the new system, to access to the frame memory for further imaging processing so as to obtain useful information for medical diagnosis. Image processing can be performed either by a special pupose processor, or by VAX 11/780. The system is made to operate asyncronously to increase the frame rate with tags assigned to the data. The proposed DSC was designed to be used without much modification for the sector scan system as well.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.124-130
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• 2014

In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. This paper presents a scan-based on-line aging monitoring scheme which monitors aging during normal operation and gives an alarm if aging is detected so that the system users take action before a failure occurs. We illustrate our modified scan chain architecture and aging monitoring control method. Experimental results show our simulation results to verify the functions of the proposed scheme.

• 대한전자공학회논문지SD
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• 제45권2호
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• pp.61-68
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• 2008

본 논문에서는 Advanced Microcontroller Bus Architecture(AMBA) 기반 System-on-Chip(SoC) 테스트를 위한 임베디드 코어 테스트 래퍼를 제시한다. IEEE 1500 과의 호환성을 유지하면서 ARM의 Test Interface Controller(TIC)로도 테스트가 가능한 테스트 래퍼를 설계한다. IEEE 1500 래퍼의 입출력 경계 레지스터를 테스트 패턴 입력과 테스트 결과 출력을 저장하는 임시 레지스터로 활용하고 변형된 테스트 절차를 적용함으로써 Scan In과 Scan Out 뿐만 아니라 PI 인가와 PO 관측도 병행하도록 하여 테스트 시간을 단축시킨다.

• 대한전기학회논문지
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• 제40권8호
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• pp.836-844
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• 1991

PLC(programmable logic controller) system is widely used for the control of factory. PLC system receives ladder diagram which is drawn by the user to implement hardware logic, converts the ladder diagram into sequence program which is executable in the PLC system, and executes the sequence program indefinitely unless user breaks. The sequence program processes the data of on/off signal, and endures 1 scan delay and missing of pulse-type signal shorter than a scan time. So, data dependency doesn't exist. By applying theis characteristics to multiprocessor architecture, we design parellel PLC functionally and evaluate performance upgrade. Parallel PLC consists of central processing module, N general processing unit, and a shared memory by master-slave type. Each module executes allocated sequence program by the control of central processing module. We can expect performance upgrade by parallel processing, and reliability by relocation of sequence program when error occurs in processing module.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.329-332
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• 2002

The traditional debug tools for chip tests and software developments need a huge investment and a plenty of time. These problems can be overcome by Embedded Debugger based the JTAG boundary Scan Architecture. Thus, the IEEE 1149.1 standard is adopted by ASIC designers for the testability problems. We designed the RED(Reusable Embedded Debugger) using the JTAG boundary Scan Architecture. The proposed debugger is applicable for not a chip test but also a software debugging. Our debugger has an additional hardware module (EICEM : Embedded ICE Module) for more critical real-time debugging.

• 한국산학기술학회논문지
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• 제10권5호
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• pp.942-946
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• 2009

ISP와 JPEG 인코더 사이에는 라스터 스캔 순서의 데이터를 $8{\times}8$ 블록 스캔 순서로 변환하는 스캔 순서 변환기가 위치한다. 최근에 단일 라인 메모리를 사용함으로써, 하드웨어 규모를 감축한 스캔 순서 변환기가 제안되었으나 매 사이클마다 기입과 독출 동작을 수행함에 따라서 전체 전력 예산의 대부분을 SRAM이 소모하는 문제점을 야기했다. 본 논문에서는 SRAM에 대한 억세스 빈도를 술이기 위하여 데이터 packer와 unpacker를 스캔 순서 변환 과정에 삽입함으로써, SRAM에 대한 억세스 빈도를 1/8로 줄이는 구조를 제안한다. 실험결과, 제안한 구조를 적용할 경우 SXGA 해 상도에서의 SRAM 전력소모량을 16% 이하로 줄어든다.

• 비파괴검사학회지
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• 제29권3호
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• pp.235-241
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• 2009

Composite wood materials are very sensitive to water and inspection without any coupling medium of a liquid is really needed to wood materials due to the permeation of coupling medium such as water. However, air-coupled ultrasound has obvious advantages over water-coupled experimentation compared with conventional C-scanner. In this work, it is desirable to perform contact-less nondestructive evaluation to assess wood material homogeneity. A wood material was nondestructively characterized with non-contact and contact modes to measure ultrasonic velocity using automated data acquisition software. We have utilized a proposed peak-delay measurement method. Also through transmission mode was performed because of the main limitation for air-coupled transducers, which is the acoustic impedance mismatch between most materials and air. The variation of ultrasonic velocity was found to be somewhat difference due to air-coupled limitations over conventional scan images. However, conventional C-scan images are well agreed with increasing the resin-infiltrated time as expected. Finally, we have developed a measurement system of an ultrasonic velocity based on data acquisition software for obtaining ultrasonic quantitative data for correlation with C-scan images.

• 전자공학회논문지C
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• 제36C권2호
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• pp.14-25
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• 1999

인쇄 회로 보드 수준의 테스팅을 위해 제안된 IEEE 표준 1149.1은 보드상의 테스트 지점에 대한 제어용이도와 관측용이도를 향상시켜 보드의 테스트를 용이하게 해준다. 그러나, 경계 주사 환경에서는 테스트 입력과 테스트 결과에 따른 데이터가 하나의 주사 연결에 의해서 직렬로 이동된다. 이는 테스트 적용시간을 증가시키고 따라서 테스트에 드는 비용을 증가시킨다. 테스트에 소모되는 시간을 줄이기 위해 병렬로 다중주사 경로를 구성하는 방법이 제안되었다. 하지만 이는 여분의 입출력 핀과 내선을 필요로 한다. 더구나 IEEE 표준 1149.1은 주사 경로 상에 있는 IC들의 병렬 동작을 지원하지 않기 때문에 표준에 맞게 설계하기가 어렵다. 본 논문에서는 하나의 테스트 버스로 두 개의 주사 경로를 동시에 제안하는 다중 주사 경로 접근 알고리즘에 기초하여 적은 면적 오버헤드를 가지고 빠른 시간 내에 보드를 테스트할 수 있는 새로운 보드수준의 내장된 자체 테스트 구조를 구현하였다. 제안된 내장된 자체 테스트 구조는 두 개의 주사 경로에 대한 테스트 입력과 테스트 결과를 이동시킬 수 있으므로 테스트에 소모되는 시간을 줄일 수 있고 또한 테스트 입력의 생성과 테스트 결과의 분석에 소모되는 비용을 줄일 수 있다.

• 대한핵의학회지
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• 제30권1호
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• pp.1-14
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• 1996

Since the publication of the first bone scintiscans in 1962 three decades have elapsed. The bone scan has made great strides during this period, becoming one of the most commonly used nuclear imaging tests. In spite of the progress, however, the specificity of bone scan has remained relatively low. As the result it is a common practice to seek additional information from radiograph, CT scan and MR image, which is euphemistically termed as "image fusion or co-location." The basic reason is the inapplicability of the classical piecemeal analysis to interpreting planar and SPECT bone scans. Such analysis has its base on the observation of elemental features of morphology, which include the size, shape, contour, location, topography and internal architecture. The physiochemical profile may well also be included. Understandably, however, the miniatured images of the planar bone scan cannot provide these features in acceptable detail and the same holds true even with SPECT Images which are but sliced views of the reconstructed planar scans. Fortunately pinhole scanning has the capacity to portray both the morphological and chemical profiles of bone and joint diseases in greater detail through true magnification. The magnitude of pinhole scan resolution is practically comparable to that of radiography as far as gross anatomy is concerned. Thus, we feel strongly that pinhole scanning is a potential breakthrough of the long-lamented low specificity of bone scan. This presentation will discuss the fun-damentals, advantages and disadvantages and the most recent advances of pinhole scanning. It high-lights the actual clinical applications of pinhole scanning in relation to the diagnosis of infective and inflammatory diseases of bone and joint.