• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1998년도 하계종합학술대회논문집
• /
• pp.429-432
• /
• 1998

The impact of hot carrier induced gate leakage current on the refresh time of memory devices has been examined. The maximum allowable supply voltage for cell transistor has been determined form the degradation of the refresh time. The desing guideline for cell capacitors and refresh circuits has been suggested.

• 대한전자공학회논문지SP
• /
• 제41권4호
• /
• pp.23-30
• /
• 2004

MPEG-4 비디오에서 움직임 적응 인트라 리프레쉬 (MAIR)는 움직임 영역을 인트라로 부호화하는 방식으로 에러의 전파를 방지한다. 움직임 영역은 이전 매크로블록과 현재 매크로블록의 영상 차이를 이용하여 결정하게 된다. AIR의 효과적인 설계는 최대 리프레쉬 시간을 줄이고 에러에 취약한 매크로블록을 예측하는 것이다. 그러나 MAIR은 인트라로 코딩할 필요성이 낮은 매크로블록도 인트라로 코딩한다. 제안한 비트율 기반의 AIR은 한 VOP에서 매크로블록 단위로 비트량을 비교하여 AIR을 수행한다. 이 방법을 사용하면 최대 리프레쉬 시간을 줄임과 동시에 에러에 취약한 매크로블록을 효율적으로 예측하여 기존의 MAIR보다 향상된 성능을 발휘한다.

• 한국멀티미디어학회논문지
• /
• 제7권12호
• /
• pp.1754-1764
• /
• 2004

Lately mobile handheld devices such as Personal Digital Assistant (PDA) and cellular phones are getting more popular for personal web surfing. However, today most mobile handheld devices have relatively poor web browsing capability due to their low performance so their users have to suffer longer communication latency than those of desktop Personal Computers (PCs). In this paper, we propose an effective pre-refresh mechanism for embedded web browser of mobile handheld devices to reduce this problem. The proposed mechanism uses the idle time to pre-refresh the expired web objects in an embedded web browser's cache memory. It increases the utilization of Central Processing Unit (CPU) power and network bandwidth during the idle time and consequently reduces the client's latency and web browsing cost. An experiment was done using a simulator designed by us to evaluate the efficacy of the proposed mechanism. The experiment result demonstrates that it has a good performance to make web surfing faster.

• ETRI Journal
• /
• 제26권6호
• /
• pp.583-588
• /
• 2004

In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of $3.63{\mu}m^2$. We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when $V_{cc}$ is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.

• IEIE Transactions on Smart Processing and Computing
• /
• 제5권2호
• /
• pp.117-122
• /
• 2016

Optimizing the number of ad clicks is a large-scale learning problem that is central to the multi-billion dollar mobile advertising industry. There are currently several optimization methods used, including ad mediation and ad positioning. This paper proposes a new method to optimize mobile advertising by using the ad refresh interval. A new metric, which can measure and compare mobile advertising performance, takes into account time limitations. The results achieved from this optimization study could maximize revenue for mobile advertisers and publishers. This research has high applicability. It also lays out a solid background for future research in this promising area.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1996년도 추계학술대회 논문집 학회본부
• /
• pp.232-234
• /
• 1996

The self-refresh mode was introduced as method to reduce power dissipation in DRAM. Because the data retention time of DRAM cell decreases as the ambient temperature rises, the internal period in self-refresh mode must be limited by retention capability at the highest temperature in DRAM specification. Because of this, at room temperature($25^{\circ}C$) unnecessary power dissipation happens, If the period of self-refresh could be modulated as temperature, it is possible to reduce the self-refresh current. In this paper, new temperature detector circuit is suggested as this purpose.

• 한국인터넷방송통신학회논문지
• /
• 제20권2호
• /
• pp.179-185
• /
• 2020

DRAM은 메인 메모리 시스템을 구성하는 주요한 요소로서 운영체제의 발전, 응용 프로그램의 복잡도와 용량의 증가에 맞추어 DRAM의 용량과 속도 역시 증가하는 추세이다. DRAM은 주기적으로 저장된 값을 읽은 후 다시 저장하는 리프레시 동작을 수행해야 하며, 이에 수반되는 성능 및 파워/에너지 오버헤드는 용량이 증가할수록 더 악화되는 특성을 내재하고 있다. 본 연구는 전하의 보존 시간이 가장 낮은 셀들에 대해서 블룸 필터를 사용하여 64ms, 128ms 이내에 리프레시를 수행해야 하는 로우들을 효율적으로 저장하여 선택적 리프레시를 수행하는 에너지 효율 향상 기법을 제안한다. 실험 결과에 따르면 제안 기법을 통하여 평균 5.5%의 성능 향상이 있었으며, 리프레시 에너지는 평균 76.4% 절감되었고, 평균 EDP는 10.3% 절감된 것으로 나타났다.

• 한국전기전자재료학회논문지
• /
• 제19권2호
• /
• pp.126-129
• /
• 2006

We investigated an optimized condition of the capacitor threshold voltage implantation(capacitor $V_T$ Implant) in planar P-MOS DRAM Cell. Several samples with different condition of the capacitor $V_T$ Implant were prepared. It appeared that for the capacitor $V_T$ Implant of $BF_2\;2.0{\times}l0^{13}\;cm^{-2}$ 15 KeV, refresh time is three times larger than that of the sample, in which capacitor $V_T$ Implant is in $BF_2\;1.0{\times}l0^{13}\;cm^{-2}$ 15 KeV. Raphael simulation revealed that the lowed maximum electric field and lowed minimum depletion capacitance ($C_{MIN}$) under the capacitor resulted in well refresh characteristics.

• 한국진공학회지
• /
• 제3권1호
• /
• pp.71-76
• /
• 1994

The electrical characteristics of the capacitor dielectric films of amorphous silicon-nit-ride-oxide(ANO) structures are compared with the capacitor dielectric films of oxide-nitride-oxide (ONO) structrues The electrical characteristics of ONO and ANO films were evaluated by high frequency(1 MHz) C-V high frequency C-V after constant voltage stree I-V TDDB and refresh time measurements. ANO films shows good electrical characteristics such as higher total charge to breakdown storage capacitance and longer refresh time than ONO films. Also it makes little difference that leakage current and flat band voltage shyift(ΔVfb)of ANO ana ONO films.

• 한국시뮬레이션학회논문지
• /
• 제9권4호
• /
• pp.51-58
• /
• 2000

The control of the data retention time is a main issue for realizing future high density dynamic random access memory. The novel junction process scheme in sub-micron DRAM cell with STI(Shallow Trench Isolation) has been investigated to improve the tail component in the retention time distribution which is of great importance in DRAM characteristics. In this' paper, we propose the new implantation scheme by gate-related ion beam shadowing effect and buffer-enhanced ${\Delta}Rp$ (projected standard deviation) increase using buffered N-implantation with tilt and 4X(4 times)-rotation that is designed on the basis of the local-field-enhancement model of the tail component. We report an excellent tail improvement of the retention time distribution attributed to the reduction of electric field across the cell junction due to the redistribution of N-concentration which is Intentionally caused by ion Beam Shadowing and Buffering Effect using tilt implantation with 4X-rotation. And also, we suggest the least requirements for adoption of this new implantation scheme and the method to optimize the key parameters such as tilt angle, rotation number, Rp compensation and Nd/Na ratio. We used MEDICI Simulator to confirm the junction device characteristics. And measured the refresh time using the ADVAN Probe tester.