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http://dx.doi.org/10.7236/JIIBC.2020.20.2.179

Techniques to improve DRAM Energy Efficiency through Selective Refresh  

Kim, Young-Ung (Dept. of Computer Engineering, Hansung University)
Publication Information
The Journal of the Institute of Internet, Broadcasting and Communication / v.20, no.2, 2020 , pp. 179-185 More about this Journal
Abstract
DRAM is a major component of the main memory system. As the operating system evolves and application complexity and capacity increases, the capacity and speed of DRAM are also increasing. DRAM should perform a refresh action of periodically reading and then re-storing stored values, and the accompanying performance and power/energy overhead embodies characteristics that worsen as capacity increases. This study proposes an energy efficiency improvement technique that efficiently stores the rows that need to be refreshed within 64ms and 128ms using the bloom filter for cells with the lowest retention time of electrons. The results of the experiment showed that the proposed technique resulted in an average 5.5% performance improvement, 76.4% reduction in average refresh energy, and 10.3% reduction in average EDP.
Keywords
DRAM; Memory Energy Performance; Refresh; Selective Refresh;
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1 Ghosh, Mrinmoy, and Hsien-Hsin S. Lee, "Smart refresh: An enhanced memory controller design for reducing energy in conventional and 3D die-stacked DRAMs", Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 134-145, Dec 2007. DOI: https://doi.org/10.1109/MICRO.2007.4408251
2 Emma, Philip G., William R. Reohr, and Mesut Meterelliyoz, "Rethinking refresh: Increasing availability and reducing power in DRAM for cache applications", IEEE Micro, Vol. 28, No. 6, pp. 47-56, Dec 2008. DOI: https://doi.org/10.1109/MM.2008.93   DOI
3 Liu, Jamie, et al., "RAIDR: Retention-aware intelligent DRAM refresh" ACM SIGARCH Computer Architecture News. Vol. 40, No. 3, Jun 2012. DOI: https://doi.org/10.1145/2366231.2337161
4 Xusheng Zhan, Yungang Bao, Ninghui Sun, "DearDRAM: Discard Weak Rows for Reducing DRAM's Refresh Overhead", 12th Conference on Advanced Computer Architecture, pp. 109-114, Aug 2018. DOI: https://doi.org/10.1007/978-981-13-2423-9_9
5 Burton H. Bloom, "Space/time trade-offs in hash coding with allowable errors", The Journal of Communications of the ACM, Vol. 13, No. 7, pp. 422-426, Jul 1970.   DOI
6 Marsaglia, George. "Xorshift rngs", The Journal of Statistical Software, Vol. 8, No. 14, pp. 1-6, 2003. DOI: https://doi.org/10.18637/jss.v008.i14
7 Carlson, Trevor E., Wim Heirmant, and Lieven Eeckhout, "Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation", Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis, pp. 1-12, Nov 2011. DOI: https://doi.org/10.1145/2063384.2063454
8 Kim, Joohee, and Marios C. Papaefthymiou, "Dynamic memory design for low data-retention power", International Workshop on Power and Timing Modeling, Optimization and Simulation. Springer, Berlin, Heidelberg, pp. 207-216, Sep. 2000. DOI: https://doi.org/10.1007/3-540-45373-3_22
9 Kim, Joohee, and Marios C. Papaefthymiou, "Block-based multiperiod dynamic memory design for low data-retention power", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 11, No. 6, pp. 1006-1018, Dec 2003. DOI: https://doi.org/10.1109/TVLSI.2003.817524   DOI
10 Chatterjee, Niladrish, et al., "Usimm: the utah simulated memory module", University of Utah, Tech. Rep pp. 1-24, 2012.
11 Standard Performance Evaluation Corporation, "SPEC CPU2006", 2006. http://www.spec.org/cpu2006/