• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
• /
• pp.563-564
• /
• 2006

Recently, CMP (Chemical Mechanical Polishing) is one of very important processing in semiconductor technology because of large integration and application of design role. CMP is a planarization process of wafer surface using the chemical and mechanical reactions. One of the most important components of the CMP system is the polishing pad. During the CMP process, the pad itself becomes smoother and glazing. Therefore it is necessary to have a pad conditioning process to refresh the pad surface, to remove slurry debris and to supply the fresh slurry on the surface. A diamond disk use during the pad conditioning. There are diamonds on the surface of diamond disk to remove slurry debris and to polish pad surface slightly, so density, shape and size of diamond are very important factors. In. this study, we characterized diamond disk with 9 kinds of sample.

• 한국재료학회:학술대회논문집
• /
• 한국재료학회 2010년도 춘계학술발표대회
• /
• pp.29.1-29.1
• /
• 2010

ZnO 는 톡특한 물리적 화학적 성질을 가지고 있는 반도성 물질이기 때문에 최근 광전자 소자인 LED, TFT, 광센서 등에 적용하려는 연구가 많은 관심을 받고 있다. 특히 1차원 ZnO 나노구조는 박막보다 높은 결정성과 물리, 화학적으로 안정하고 표면적이 매우 넓어 많은 연구가 진행되고 있지만, 대량으로 간단하며 저렴하게 생산하기 위해서 친환경적이며 적은 시간으로 합성을 해야 한다. 그래서 최근 수열 합성법을 이용하여 합성이 많이 이루어지고 있지만, ZnO 나노막대 제조 중 기존에 보고된 방법은 대부분 aspect ratio가 낮으며, 저가의 용액 기반으로 높은 aspect ratio를 가지는 나노 선을 제작하기 어려운 실정이다. 또한 용액기반의 성장에서는 기판과의 격자 상수와 열팽창 계수의 차이로 인해 기판과의 adhesion 이 매우 낮아 adhesion layer를 증착 하여 나노 막대을 제작하는 것이 발표가 되고 있다. 하지만 또 하나의 공정이 더해지기 때문에 복잡해지고, 소자에 응용하기에는 한계점이 보인다. 그렇기 때문에 이번 연구에서는 성장 시 Zn 소스가 소모가 다 되었을 시 성장 용액을 교체하는 과정에서 성장 온도와 같이 유지 시킨 뒤에 성장을 하는 방법으로 수직 방향으로 10 um 의 길이를 가지는 ZnO 나노막대의 합성을 가능하게 하였다.

• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 2005년도 ICCAS
• /
• pp.1107-1111
• /
• 2005

This paper presents a design of Programmable logic Controllers which are well known for a long time that can be applied to be a controller for an automatic machine in industries. However, most of them have been imported from oversea country. This research focuses on the development of PLC by KMITL staff. This PLC system is consists of CPU unit, Digital I/O RTU unit, ANALOG RTU unit. The implementation of the CPU scan time and I/O refresh are principle to PLC. In this article, there are many benefits to industries especially in order to support SME that can use local technology. Therefore, we can apply this research to the manufacturing process in Thailand for the future.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제16권6호
• /
• pp.781-792
• /
• 2016

This paper presents a new approach to enhance the data retention of logic-compatible embedded DRAMs. The memory bit-cell in this work consists of two logic transistors implemented in generic triple-well CMOS process. The key idea is to use the parasitic junction capacitance built between the common cell-body and the data storage node. For each write access, a voltage transition on the cell-body couples up the data storage levels. This technique enhances the data retention and the read performance without using additional cell devices. The technique also provides much strong immunity from the write disturbance in the nature. Measurement results from a 64-kbit eDRAM test chip implemented in a 130 nm logic CMOS technology demonstrate the effectiveness of the proposed circuit technique. The refresh period for 99.9% bit yield measures $600{\mu}s$ at 1.1 V and $85^{\circ}C$, enhancing by % over the conventional design approach.

• 한국조경학회지
• /
• 제13권2호
• /
• pp.27-36
• /
• 1985

^x In Korea, we are entering on a new phase that the use concept of urban park is extending to dynamic activities such as games and sports. This article is to investigate the significance of lawn areas, as a receptive space of such a wide range of recreation activities. As a study process, Green Styles (type of parks) such as Garden Type, Park Type and Forest Type were studied and historical review of lawn areas in park development was performed. In conclusion, the lawn areas ( greensward) are an essential part of park and open space organization. The significance as a conclusion is presented as follows : 1 ) Balance in type of parks The structures of our parks and open spaces are inclined toward the artificial Garden Type and natural Forest Type. Therefore, the intermediate Park Type and sparse wood areas should be a core part of our park and open space development. 2) Psychological effect Park Type areas, thorned by greensward(lawn area), can refresh urban dwellers with natural picturesque landscaps, and Park Type landscape is the most preferred natural landscape. It shows the essence of natural amenity as 3) Accomodation of wide range of recreation activities Lawn areas in urban park are the best place in accomodating the wide range of active and massive recreation activities. Thus, lawn areas can increase the freedom of recreation use in urban park. 4) Enlargement of physical carrying capacity. With expansion of lawn areas of euro- american concept, the structural open space can be transformed into service open space. Thus, the recreation carrying capacity of urban parks can be enlarged.

• 한국건설관리학회논문집
• /
• 제15권1호
• /
• pp.20-27
• /
• 2014

효과적인 건설안전교육을 위해서는 기존의 문서와 시청각자료에 의존한 이론적인 수업방법에서 벗어나, 체험위주의 교육과 실무중심의 교육이 필요하다. 본 연구에서는 가상현실환경을 구현할 수 있는 3D엔진을 사용하여 건설현장 및 학교에서 안전교육용으로 사용할 수 있는 기능성게임을 개발하였다. 학습자는 게임 내에서 가상공간 내의 건설현장을 돌아다니며 잠재적인 안전재해 발생요인을 발견하는 안전관리자의 역할을 수행하게 된다. 이러한 시행착오 과정을 통해 안전에 관련된 지식을 학습자 스스로 익히게 된다. 또한 게임과정에서 학습과정을 돕기 위해 피드백이 제공되며, 획득한 포인트를 바탕으로 성과를 평가하게 된다. 학생들을 대상으로 한 평가에서 기능성 게임을 통한 안전교육은 설계과정에서 계획된 효과들을 이룬 것으로 나타났으며, 학습자들에게 긍정적인 효과를 나타내 것으로 평가되었다.

• 한국컴퓨터산업학회논문지
• /
• 제6권5호
• /
• pp.757-766
• /
• 2005

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6T Full CMOS SRAM had been continued as the technology advances, However, conventional 6T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6T Full CMOS SRAM is $70{\sim}90F^{2}$, which is too large compared to $8{\sim}9F^{2}$ of DRAM cell. With 80nm design rule using 193nm ArF lithography, the maximum density is 72M bits at the most. Therefore, pseudo SRAM or 1T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed $S^{3}$ cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^{3}$ SRAM cell technology with 100nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• 한국전기전자재료학회논문지
• /
• 제19권4호
• /
• pp.314-321
• /
• 2006

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6 T Full CMOS SRAM had been continued as the technology advances. However, conventional 6 T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6 T Full CMOS SRAM is $70{\sim}90\;F^2$, which is too large compared to $8{\sim}9\;F^2$ of DRAM cell. With 80 nm design rule using 193 nm ArF lithography, the maximum density is 72 Mbits at the most. Therefore, pseudo SRAM or 1 T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64 M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6 T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S3 cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^3$ SRAM cell technology with 100 nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• 대한전자공학회논문지SD
• /
• 제37권4호
• /
• pp.15-24
• /
• 2000

고유전 커패시터의 유전완화 특성은 시간영역에서 나타나는 커패시터의 동적특성으로 이해될 수 있으며 이것은 DRAM의 재충전 시간동안 충전된 전하를 잃어버리는 가장 주된 요인으로 인식된다. 그러므로 DRAM 동작에 미치는 영향을 고려하기 위하여 고유전 커패시터의 유전완화에 대한 등가회로를 만드는 것이 필수적이다. 그러나 아직까지 등가회로를 만들 수 있는 일반적이고 이론적인 방법이 제시되지 않고 있다. 근 본 연구에서는 고유전 커패시터의 등가회로를 주파수 영역에서 모델링하는 새로운 방법을 개발하였다. 이 방법은 이론적인 체계를 갖춘 일반적인 방법이다. 또한, 본 연구에서는 실험과정을 통해서 이 방법의 타당성으로 확인하였고, 궁극적으로 새로운 방법으로 얻어진 등가회로를 활용하여 유전완화가 DRAM 동작에 미치는 영향을 고찰하였다.

• Journal of Biosystems Engineering
• /
• 제34권4호
• /
• pp.278-285
• /
• 2009

Navigation system is applied in variety of fields including the simple location positioning, autopilot navigation of unmanned robot tractor, autonomous guidance systems for agricultural vehicles, construction of large field works that require high precision and map making process. Particularly utilization of GPS (Global Positioning System) is very common in the present navigation system. This study introduces a navigation system for autonomous field robot that travels to the pre-input path using GPS information. Performance of the GPS- based navigation is highly depended on its receiving rate because GPS receivers do not acquire any navigation information in the period between the refresh intervals. So this study presents an algorithm that improves an accuracy of the navigation by estimation the positional information during the blind period of a low rate GPS receiver. In fact the algorithm calculated the robot's heading in a 50 Hz rate, so the blind period of an 1 Hz GPS receiver is extensively covered. Consequently implementation of the algorithm to the GPS based navigation showed an improvement in guidance accuracy. The conventional field robot directly carried an expensive control computer and sensors onboard, therefore the miniaturization and weight reduction of the robot was limited. In this paper, the field robot carried only communication equipments such as GPS module, normal RC receiver, and bluetooth modem. This enabled the field robot to be built in an economic cost and miniature size.