Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Circuit Model of the Dielectric Relaxation of the High Dielectric $(Ba,Sr)Tio_3$ Thin Film Capacitor for Giga-Bit Scale DRAMs

Giga-Bit급 DRAM을 위한 고유전 $(Ba,Sr)Tio_3$박막 커패시터의 유전완화 특성에 대한 회로 모델

  • Jang, Byeong-Tak ;
  • Cha, Seon-Yong (Dept. of Electrical Eng. and Electronic Eng., Korea advanced Institute of Science and Technology) ;
  • Lee, Hui-Cheol (Dept. of Electrical Eng. and Electronic Eng., Korea advanced Institute of Science and Technology)
  • 장병탁 (삼성전자주식회사 메모리 사업부) ;
  • 차선용 (한국과학기술원 전기 및 전자공학과) ;
  • 이희철 (한국과학기술원 전기 및 전자공학과)
  • Published : 2000.04.01
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Abstract

The dielectric relaxation of high-dielectric capacitors could be understood as a dynamic property of the capacitor in the time domain, which is regarded as a primarily important charge loss mechanism during the refresh time of DRAMs. Therefore, the equivalent circuit of the dielectric relaxation of the high-dielectric capacitor is essentially required to investigate its effects on DRAM. Nevertheless, There is not any theoretical method which is generally applied to realize the equivalent circuit of the dielectric relaxation. Recently, we have developed a novel procedure for the circuit modeling of the dielectric relaxation of high-dielectric capacitor utilizing the frequency domain. This procedure is a general method based on theoretical approach. We have also verified the feasibility of this procedure through experimental process. Finally, we successfully investigated the effect of dielectric relaxation on DRAM operation with the obtained equivalent circuit through this new method.

고유전 커패시터의 유전완화 특성은 시간영역에서 나타나는 커패시터의 동적특성으로 이해될 수 있으며 이것은 DRAM의 재충전 시간동안 충전된 전하를 잃어버리는 가장 주된 요인으로 인식된다. 그러므로 DRAM 동작에 미치는 영향을 고려하기 위하여 고유전 커패시터의 유전완화에 대한 등가회로를 만드는 것이 필수적이다. 그러나 아직까지 등가회로를 만들 수 있는 일반적이고 이론적인 방법이 제시되지 않고 있다. 근 본 연구에서는 고유전 커패시터의 등가회로를 주파수 영역에서 모델링하는 새로운 방법을 개발하였다. 이 방법은 이론적인 체계를 갖춘 일반적인 방법이다. 또한, 본 연구에서는 실험과정을 통해서 이 방법의 타당성으로 확인하였고, 궁극적으로 새로운 방법으로 얻어진 등가회로를 활용하여 유전완화가 DRAM 동작에 미치는 영향을 고찰하였다.

Keywords

References

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