• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.6
• /
• pp.867-872
• /
• 2016

We have investigated the channel mobility of AlGaN/GaN-on-Si recessed-metal-oxide-semiconductor-heterojunction field-effect transistors (recessed-MOS-HFET) with $SiO_2$ gate oxide. Both field-effect mobility and effective mobility for the recessed-MOS channel region were extracted as a function of the effective transverse electric field. The maximum field effect mobility was $380cm^2/V{\cdot}s$ near the threshold voltage. The effective channel mobility at the on-state bias condition was $115cm^2/V{\cdot}s$ at which the effective transverse electric field was 340 kV/cm. The influence of the recessed-MOS region on the overall channel mobility of AlGaN/GaN recessed-MOS-HFETs was also investigated.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.48 no.9
• /
• pp.605-610
• /
• 1999

An SOI(Silicon-On-Insulator) LD(Lateral Double-diffused)MOS with a recessed source structure is proposed to improve the on-resistance and the breakdown voltage. The recessed source structure can decrease the on-resistance by reducing the path of electron current, also increase the breakdown voltage by extending the effective length of gate field plate. Simulation results by TSUPREM4 and MEDICI have shown that the on-resistance of the LDMOS with a recessed source was 26% lower than conventional LDMOS. The breakdown voltage of proposed device was found to be 45V while that of conventional device was 36.5 V. At the same breakdown voltage of 36.5V, the on-resistance of the LDMOS with a recessed source was 41% lower than that of conventional structure.

• Journal of IKEEE
• /
• v.11 no.4
• /
• pp.247-251
• /
• 2007

The recessed gate IGBT has a lower on-state voltage drop compared with the DMOS IGBT, because there is no JFET resistance. But because of the electric field concentration in the corner of the gate edge, the breakdown voltage decreases. This paper is about the new structure to effectively improve the Vce(sat) voltage without breakdown voltage drop in 1700V NPT type recessed gate IGBT with p floating shielding layer. For the fabrication of the recessed gate IGBT with p floating shielding layer, it is necessary to perform the only one implant step for the shielding layer. Analysis on the Breakdown voltage shows the improved values compared to the conventional recessed gate IGBT structures. The result shows the improvement on Breakdown voltage without worsening other characteristics of the device. The electrical characteristics were studied by MEDICI simulation results.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.7
• /
• pp.149-155
• /
• 1996

A new technique wasdeveloped which obtains selectively the htick fully recessed oxidized porous silicon layer (OPSL) with good dielectric property. The porous silicon layer was ocnverted to thick fully recessed oxide (FRO) with 3-step (1${\mu}$m, 1.5${\mu}$m, 1.8${\mu}$m) by multi-step thermal oxidation (after 400$^{\circ}$C, 1 hour by dry oxidation, 700$^{\circ}$C, 1 hour and then 1100$^{\circ}$C, 1 hour by wet oxidation). The breakdwon field of the FRO was about 2.5MV/cm and the leakage current was several pA ~ 100 pA in the range of 0 of 90 pF. The progress of oxidation of a porous silicon layer was studied by examining the infrared abosrption spectra. The refractive index (1.51) of the fRO, which was measured by ellipsometer, was comparable to that of the thermally grown silicon dioxide (1.46). The etching rate (1600${\AA}$/min) of the FRO was also almost equal to that of the thermal oxide.

• Proceedings of the KIEE Conference
• /
• 2001.07c
• /
• pp.1451-1453
• /
• 2001

An SOI(Silicon-On-Insulator) LD(Lateral Double-diffused)MOS with graded gate and recessed source is proposed. The proposed structure can increase the breakdown voltage by reducing the electric field crowding at the edge of gate. Simulation results by TSUPREM4 and MEDICI have shown that the breakdown voltage of proposed device was found to be 52 V while that of conventional device was 45 V. At the same breakdown voltage of 45 V, the on-resistance of the LDMOS with graded gate and recessed source was 14.4 % lower than that of conventional structure.

• Wind and Structures
• /
• v.38 no.3
• /
• pp.193-202
• /
• 2024

Modern high-rise tower designs incorporating recessed balcony cavity spaces can be prone to high-frequency and narrow-band Rossiter aerodynamic excitations under glancing incident winds that can harmonize and compete with recessed balcony volume acoustic Helmholtz modes and facade elastic responses. Resulting resonant inertial wind loading to balcony facades responding to these excitations is additive to the peak design wind pressures currently allowed for in wind codes and can present as excessive facade vibrations and sub-audible throbbing in the serviceability range of wind speeds. This paper presents a methodology to determine Cavity Amplification Factors to account for façade resonant inertial wind loads resulting from balcony cavity aero-acoustic-elastic resonances by drawing upon field observations and the results of full-scale monitoring and model-scale wind tunnel tests. Recessed balcony cavities with single orifice type openings and located within curved façade tower geometries appear particularly prone. A Cavity Amplification Factor of 1.8 is calculated in one example representing almost a doubling of local façade design wind pressures. Balcony façade and tower design recommendations to mitigate wind induced aero-acoustic-elastic resonances are provided.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.3
• /
• pp.169-181
• /
• 2011

In this present paper, a comprehensive drain current model incorporating the effects of channel length modulation has been presented for multi-layered gate material engineered trapezoidal recessed channel (MLGME-TRC) MOSFET and the expression for linearity performance metrics, i.e. higher order transconductance coefficients: $g_{m1}$, $g_{m2}$, $g_{m3}$, and figure-of-merit (FOM) metrics; $V_{IP2}$, $V_{IP3}$, IIP3 and 1-dB compression point, has been obtained. It is shown that, the incorporation of multi-layered architecture on gate material engineered trapezoidal recessed channel (GME-TRC) MOSFET leads to improved linearity performance in comparison to its conventional counterparts trapezoidal recessed channel (TRC) and rectangular recessed channel (RRC) MOSFETs, proving its efficiency for low-noise applications and future ULSI production. The impact of various structural parameters such as variation of work function, substrate doping and source/drain junction depth ($X_j$) or negative junction depth (NJD) have been examined for GME-TRC MOSFET and compared its effectiveness with MLGME-TRC MOSFET. The results obtained from proposed model are verified with simulated and experimental results. A good agreement between the results is obtained, thus validating the model.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.8 no.1
• /
• pp.11-20
• /
• 2008

The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the $V_{th}$ margin for 2-bit/cell operation by ${\sim}2.5$ times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the $V_{th}$ margin more than ${\sim}1.5V$. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better ${\Delta}V_{th}$ and $V_{th}$ margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ${\sim}10nm$ below the source/drain junction.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.5
• /
• pp.554-562
• /
• 2015

This paper presents the design and analysis of gate-recessed AlGaN/GaN Fin-type Field-Effect Transistor (FinFET). The three-dimensional (3-D) technology computer-aided design (TCAD) simulations were performed to analyze the direct-current (DC) and radio-frequency (RF) characteristics for AlGaN/GaN FinFETs. The fin width ($W_{fin}$) and the height of GaN layer ($H_{GaN}$) are the design parameters used to improve the electrical performances of gate-recessed AlGaN/GaN FinFET.

• Journal of the Korean Society of Propulsion Engineers
• /
• v.16 no.1
• /
• pp.55-63
• /
• 2012

The turbulent flow characteristics in a coaxial injector were investigated by the nonlinear $k-{\varepsilon}-f_{\mu}$ model of Park et al.[1] and large eddy simulation (LES). In order to analyze the geometric effects on the scalar mixing for nonreacting variable-density flows, several recessed lengths and momentum flux ratios are selected at a constant Reynolds number. The nonlinear $k-{\varepsilon}-f_{\mu}$�� model proposed the meaningful characteristics for various momentum flux ratios and recess lengths. The LES results showed the changes of small-scale structures by the recess. When the inner jet was recessed, the development of turbulent kinetic energy became faster than that of non-recessed case. Also, the mixing characteristics were mainly influenced by the variation of shear rates, but the local mixing was changed by the adoption of recess.